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Boundary Scan JTAG

FPGA Configuration BIST embedded JTAG
» TEST-IP Brochure

» SystemBIST Overview
» FAC Overview
» SRL Overview

JTAG DFT Design-for-Test

Boundary Scan (DFT) Design-for-Test is easy with Intellitech's TEST-IP Family

The TEST-IP Family is patented infrastructure Intellectual Property. The IP is embedded into a design, provided as an IC or temporarily loaded into an FPGA. The appraoch provides a scalable, re-usable and unified configuration and test methodology, which enables design teams to produce high-quality self-testable and in-the-field re-configurable products that are tamper resistant. Since there is a clear seperation of design and support infrastructure, each generation product can re-use the infrastructure without re-integration and re-work

JTAG DFT Embedded Built in Self Test BIST

TEST-IP Infrastructure

The Infrastructure IP is independent of the functional design and takes the form factor of an individual IC, soft macro or binary bitstream for embedding in FPGA/CPLD devices. The TEST-IP family provides pre-engineered and proven infrastructure for embedded configuration and test, fast in-system FLASH programming and scan chain management for PCB and systems.

Unified Configuration and Test using IEEE 1149.1 (JTAG)

The TEST-IP Family leverages the IEEE 1149.1 industry standard test bus as a single unified data (configuration and test) application vehicle. This unified approach to configuration and test lowers manufacturing test costs, simplifies field support and extends a product's useful life. The TEST-IP infrastructure IP is scalable and can be reused during all phases of the product life cycle and from one product design to the next.

EclipseTM Test Development Environment Supports TEST-IP

Device configuration data and embedded manufacturing tests are created and validated using the Eclipse Test Development Environment. The verified data is loaded into FLASH memory and applied to the system at power-up using the IEEE 1149.1 test bus.

TEST-IP Family of Infrastructure IP Products

The SystemBISTTM configuration and self-test devices- is a complete plug-and-play IP module built upon a unique patented architecture. The SystemBIST device is embedded onto a PCB, which enables design engineers to build high quality, self-testable and in-the-field re-configurable products. SystemBIST is vendor independent and can configure any IEEE 1532 or IEEE 1149.1 compliant FPGA and CPLD in-system.

The Fast Access Controller FACTM - is a patented pre-engineered IP solution for processor (Micro-controller, DSP or CPU) and ASIC/SoC designers who need to respond to customer demands for better Design-for-Test and improved support and programming performance for external FLASH in a production environment. The FAC provides the fastest way to program on-board Flash memory, especially when it is connected to an FPGA. A small bitstream is loaded which enables the FLASH to receive programming data over the 1149.1 bus.

The Scan Ring Linker SRLTM - is a complete IP module that can be easily embedded into a CPLD, FPGA or ASIC on a PCB to reduce the complexities and costs of designing 1149.1 (JTAG) test infrastructure for designs that use multiple scan rings. The SRL IP module links any number of scan rings (secondary scan paths) into a single high-speed test bus, which permits devices on secondary scan chains to be independently tested and configured through a single 1149.1 external interface.

TEST-IP Family Benefits

  • TEST-IP is a 'codeless' plug-and-play infrastructure that can configure any IEEE 1532 compliant programmable device in-system from a single source
  • TEST-IP significantly reduces product parts cost (eliminates FPGA configuration PROMs and voltage translators parts on multi-scan chain design)
  • TEST-IP family lessens the time spent on designing ad-hoc mechanisms for in-system device configuration and programming, system bring-up and debug, board interconnect test and at-speed memory test
  • TEST-IP can execute deterministic embedded test at anytime and anywhere without the need to be connected to ATE
  • TEST-IP reduces in-system FLASH programming times
  • TEST-IP is fully integrated with the Eclipse Test Development Environment so that configuration and test suites can be created and validated before they are committed to the system