1149.1 (JTAG) Mux Switch

The SRL is a complete plug-and-play IC that can be easily incorporated on a PCB to reduce the complexities and costs of designing IEEE 1149.1 test infrastructure for designs that use multiple scan rings. The SRL links any number of scan rings (secondary scan paths) into a single high-speed test bus, which permits devices on secondary scan chains to be independently tested and configured through a single IEEE 1149.1 external interface. This dramatically shortens scan operations and thus enables the fastest on-board FLASH programming and in-system configuration times.

The SRL provides proper buffering of test signals to reduce the need for external logic and complex interfaces between boundary-scan devices that require different input voltages. SRL is IEEE 1149.1 compliant, fully testable and fulfills all of the requirements for multi-chain PCB design. SRL is highly cost-effective because it eliminates the need to incorporate special buffers and voltage level translator components on a board.

If you need multi-PCB or system-wide JTAG chain linking then please see PTC - Addressable JTAG for Parallel Test & Configuration

The SRL creates a Single Test Interface for multi-voltage scan-chains

Challenges of using complex scan chains

To reduce test and in-system device programming times designers often use multiple scan chains. This enables a single long scan chain to be broken up into smaller chains that are more efficient. Programming and configuration times for FLASH and FPGA devices can be shortened if the devices are placed on smaller scan chains. In many cases, in-system configuration of FPGAs cannot take place unless they are completely isolated in a separate scan chain from other functional logic.

Accommodating multiple voltage level ICs requires the designer to add voltage translators. Commercial Scan Path Linkers from TI and ScanBridge from NSC have been used as a method of accommodating multiple scan paths. The devices pose significant problems to test engineers who use third party IEEE 1149.1 test development tools. Users are forced into significant manual intervention in order to debug and get working manufacturing tests. These devices also do not support today's lower voltage designs. Signal Integrity must be addressed in the distribution of TCK, TMS and TRST signals. Design and test complexity increases significantly and IEEE 1149.1 expertise is required to integrate and test the system.

The Scan Ring Linker is a plug and play solution for designers who use multiple scan chains

The high fanout and voltage translation fulfills all of the requirements for multi-chain PCB design. The SRL is cost-effective because it eliminates the need to incorporate special buffers and voltage level translator components on the board. The SRL is fully configurable, completely IEEE 1149.1 compliant so it removes the requirement to design and implement a complicated customized test implementation that may not be testable itself. The SRL pins themselves are fully testable for shorts enhancing fault coverage and diagnostics when scan path problems exist.  

The SRL in conjunction with the Eclipse Test Development Environment reduces design bring-up time because it can make system debug using ICE and OCD methodologies much more efficient.

Benefits of the SRL Technology

Reduces part costs

SRL can be deployed as a single IC on a PCB to reduce the need for scan chain buffers and logic level translators. SRL permits devices in secondary scan chains to have their IO pins configured at different voltage levels. A single SRL device controls each scan chain regardless of their voltage.

Better signal integrity

TCK TMS TRST TDI TDO