Multiple Scan Chains

Problem

To reduce test and in-system device programming times designers often use multiple scan chains to shortened the number of test clock cycles required to program a FLASH or CPLD device in-system.

There are several challenges designing a system or PCB with multiple scan chains

1. Accommodating multiple voltage level ICs requires the designer to add voltage translators
2. Signal Integrity must be addressed in the distribution of TCK, TMS and TRST signals
3. Older solutions such as TI Scan Path Linker 74LVT8997 or National Semiconductor Scan Bridge PSC110/PSC111 are single voltage with TCK and TMS distribution 
4. Design and test complexity increases significantly and IEEE 1149.1 expertise is required to integrate and test the system

Embedded Scan Ring Linker^TM (SRL^TM) Creates a Single High-Speed 1149.1 Test Bus Solution

 

NSC Scan Bridge PSC111 and TI 8996 Scan Path Linker Replacement

SRL Creates a Single Test Interface for Multiple Voltage Devices

The ideal solution provides the design engineer with plug-and-play IP module that can be easily embedded into a CPLD, FPGA or ASIC on a PCB to reduce the complexities and costs of designing 1149.1 test infrastructure for designs that use multiple scan rings.

To implement this methodology Intellitech provides the TEST-IP^TM family of patent-pending Infrastructure Intellectual Property (IP) modules.

The SRL IP module links any number of scan rings (secondary scan paths) into a single high-speed test bus, which permits devices on secondary scan chains to be independently tested and configured through a single 1149.1 external interface. This dramatically shortens scan operations and thus enables maximum data throughput.

SRL simplifies design of a multi-scan chain system

1. The SRL can be embedded into an existing CPLD or FPGA and can be configured to accommodate multiple voltage levels on N number of scan chains
2. Pre-designed SRLs with 4 through 12 scan chains are ready to drop in to VQ64, QFP and BGA packages
3. SRL handles distribution of multiple copies of TCK, TMS and TRST signals on local scan paths
4. All SRL pins are fully testable for shorts and bridging faults across 1149.1/JTAG signals (TCK, TMS, TDI, TDO) with the Eclipse^TM Test Development Environment
5. All SRL pins are configurable to target 1.8V-5V operation
6. SRL is part of an embedded configuration and test solution that supports an entire system in the lab, in manufacturing and in the field