Please Log in (Forgot) or Register boundary scan jtag test
Boundary Scan JTAG
scan linker
jtag multiplexer

» TEST-IP Overview
» SRL Overview

System JTAG Linking without STA112
SRL Datasheet and Online ordering

The JTAG Linking Problem

To reduce test and in-system device programming times designers often use multiple scan chains to shortened the number of test clock cycles required to program a FLASH or CPLD device in-system.

There are several challenges designing a system or PCB with multiple scan chains

  • Signal Integrity must be addressed in the standard bussed distribution of TCK, TMS and TRST signals when Point-to-Point signals are known to have better SI (no stubs, split impedences etc)
  • It's desired to use series termination at the driver of TCK due to the better performance, but 1149.1 bussed topology with multiple end-points is not compatible with series termination.
  • TCK Skew throughout the system narrows the window of operation due to setup/hold times of TMS and TDI limiting overall JTAG scan rates.
  • Older solutions such as TI Scan Path Linker 74LVT8997 or National Semiconductor Scan Bridge STA112, STA111, PSC111 are single voltage with single  TCK and TMS distribution  per path
  • Ad-hoc designs with multiple MSI packages result in many non-testable points of JTAG chain failure
  • Multiple MSI packages increases cost of stocking, ordering and decreases layout area.
  • Test complexity increases significantly with single path ad-hoc designs and IEEE 1149.1 expertise is required to integrate and test the system
  • Accommodating multiple voltage level ICs requires the designer to add voltage translators on JTAG
  • Ad-hoc design energy is repeated for each PCB designed by the company

Embedded Scan Ring LinkerTM creates a single High-Speed 1149.1 Test Bus
NSC Scan Bridge STA112 and TI 8996 Scan Path Linker Replacement

SRL Creates a Single Test Interface for complex PCBs

The ideal solution provides the design engineer with plug-and-play IC that can be easily embedded into a PCB or System to reduce the complexities and costs of designing 1149.1 test infrastructure for designs that use multiple scan rings.

The SRL links 4 to 14 scan rings (depending on package) into a single high-speed test bus, which permits devices on secondary scan chains to be independently tested and configured through a single 1149.1 external interface. This dramatically shortens scan operations and thus enables maximum data throughput. The SRL enables multi-PCB systems to be linked together for a System JTAG level test.

Find out how Intellitech's SRL helped Polycom test a complex multi-PCB system with FPGAs, DSPs and SERDES here: Scan Chain Routing Multiplexer

Link JTAG chains or rings

SRL simplifies design of a multi-scan chain system

  • SRL handles distribution of multiple copies of TCK, TMS and TRST signals on local scan paths
  • All SRL pins are fully testable for shorts and bridging faults across 1149.1/JTAG signals (TCK, TMS, TDI, TDO) with the EclipseTM Test Development Environment
  • All SRL pins are configurable to target 1.8V-5V operation
  • SRL as part of an embedded configuration and test solution that supports an entire system in the lab, in manufacturing and in the field
  • The SRL is available in Comercial, Industrial and AECQ qualified parts. Rohs-5 or Rohs-6 compliant