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JTAG programming software
Boundary Scan JTAG
on-board programming
on-board programming
On-Board Programming

FLASH Backgrounder
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TEST-IP Overview

On-Board Programming with the Fast Access Controller and FLASH 

To program a FLASH memory, FAC takes the streaming serial data (FLASH program data) from the 1149.1 scan chain and delivers it to the programmable memory interface so it can be written to the FLASH memory directly. FAC contains patent-pending circuitry to control memories so it does not require that the Write/Read programming protocol or the memory address to be transmitted in the serial bit stream. The patent-pending method avoids using the boundary-scan register for programming external FLASH.  These features enable the FAC IP to write/read FLASH at the full speed of FLASH device using data delivery as slow as 3mbits/sec.  FAC can also program serial EEPROMs at-speed in a similar manner. 

The FAC can also be used For Memory Test

The FAC IP contains a programmable sequence generator and flexible memory controller.  The FAC can be configured over the IEEE 1149.1 bus to perform read and write operations to a variety of memory devices.  This enables in-system at-speed memory interconnect tests for SRAM, DRAM, DDRAM or any other type of RAM architectures.  A smaller dedicated FAC IP can also be programmed temporarily into an FPGA to perform the same types of FLASH programming or memory test. At the successful completion of the memory testing the FAC can be "erased" and the functional design can be loaded into the FPGA over the IEEE 1149.1 bus.