Intellitech continues its leadership position with these peer-reviewed conference papers and invited presentations.
International Test Conference Sept 19, 2011
"IEEE 1149.1-2012 update". Proposed changes enable test re-use for the life-cycle of 1149.1 compliant IP and ICs. Slides explain importance of ecosystem test, correlation, test re-use, and strategies for in-situ test followed by syntax examples of BSDL on-chip register fields and PDL language
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ITC Nov 2nd, 2010
"SOLUTIONS FOR UNDETECTED SHORTS ON IEEE 1149.1 SELF-MONITORING PINS" ITC Conference Paper
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| EDN article - "Managing Multiple-Bitstreams for remote system updates". |
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HOST 2010 Invited Panelist
"The Challenges of Trojan Insertion" - Are we focused on the right problem? |
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SoC Debug Workshop DAC 2010
"IEEE P1687 Basics - Standard for Access and Control of Instrumentation embedded within a semiconductor device" Invited presentation |
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Hardware Oriented Security and Trust - HOST 2010
"Anti-tamper JTAG TAP design enables DRM to JTAG registers and P1687 on-chip instruments"
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NATW May 2010
Introduction to P1687/IJTAG
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VLSI Test Symposium, April 2010.
iMajik: Making 1149.1 TAPs disappear and reappear in SoCs and 3D packages. |
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| "The Impact of Nanometer Technologies on Manufacturability on Yield", CEO CJ Clark is invited speaker at DATE 2010 executive panel. |
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Board Test Workshop 2009
Micropin Vertical Fixtures for High Volume PCB Test using JAF (JTAG Assisted Functional Test) |
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Chip Design Magazine
The benefits of SystemBIST FPGA configuration is highlighted in the article "Managing Multiple Bitstream Images..." by Neil Jacobson in Chip Design. |
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HOST July 27th, 2009
Secure hardware: What are the BIG challenges?“ at 2nd IEEE International Workshop on Hardware-Oriented Security and Trust
A short panel presentation on some of the challenges |
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DesignCon February 4th, 2009
Business Considerations for RAM-based FPGA configuration
This paper discusses FPGA security, anti-hacking, Built-in-Test and the cost of engineering |
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FPGA Summit December 9, 2008 :
FPGA Bitstream Authentication and FPGA security Powerpoint |
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FPGA Summit December 9, 2008 :
FPGA Bitstream Authentication and FPGA Security |
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Featured Interview on EG3.COM Nov 12, 2008 :
Interview with CEO CJ Clark on FPGA Ecosystems |
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IJTAG Presentation Nov 10, 2008 :
IJTAG Language Position |
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Board Test Workshop 2006 :
CJTAG : Enhancement to IEEE 1149.1 uses concurrent test to reduce test times |
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International Test Conference 2004:
A Codeless
BIST Processor for Embedded Test
and in-system
configuration of Boards and Systems
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The Future of ATE 2003:
Scalable Tester Architecture for Structural Test of Wafers and packaged ICs
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IEEE Design and Test Article:
Infrastructure IP for
Configuration and Test of Boards and Systems
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BTW'03
An Embedded Test and
Configuration Processor for Self-Testable and
Field Re-Configurable
Systems
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BTW'03
A Fast Access Controller for
In-System Programming of FLASH Memory
Devices
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Infrastructure IP workshop '03:
Infrastructure IP for programming and test of in-system devices |
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DATE 2003 CEO Panel
The presentation that started getting the industry to look at the power of on-chip JTAG. CJ Clark's predictions for the use of Internal JTAG back in 2003 including on-chip BERT for SERDES, on-chip monitors for IC health, limitations of system functional test and more.
Moderator: Nic Mokhoff, EE Times and Yervant Zorian, Vice President and Chief Scientist Virage Logic
Executive Panelists:
Vinod Agarwal - LogicVision, Inc.
Roger Blethen - LTX Corporation
Christopher J. Clark - Intellitech Corporation
Antun Domic - Synopsys, Inc.
Robert Hum - Mentor Graphics Corporation
Paul Sakamoto - Inovys Corporation
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OTW 2002
"The future of boundary scan test - At-speed testing"
The predictions of 2002 continue to be true today. |
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OTW 2002
Embedded Test Structures - At-speed tests using embedded 'helper' circuits
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VTS 2002
Reducing Time to Volume and Time to Market: Is Silicon Debug and
Diagnosis the Answer ? |
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