FPGA Programming and CPLD Configuration
Many products must adapt to changing customer requirements, new industry standards, bug fixes and engineering enhancements. The ability to upgrade programmable system logic (FPGAs, CPLDs) and memories (EEPROM, FLASH) from a centralized point to address this issue can significantly extend a product's useful life.
The method that is predominately used to
configure programmable logic employs special electrically alterable
configuration PROMs. These PROMs
are programmed with a design that is loaded into the FPGA at power-up. Alternatively, a FLASH memory and a CPLD can be custom designed to configure 1-4 FPGAs using the FPGA vendor's proprietary progamming method such as SelectMAP.
There are other significant challenges with current configuration techniques for systems that use multiple FPGAs and CPLDs
- On average, a large FPGA can require up
to three erasable PROMs for configuration which impacts PCB part
cost and requires significant board space
- Erasable configuration PROMS are costly, $20-$30 even in reasonable volumes
- PROMs employ a proprietary method for programming the FPGAs so they are not interchangeable between different programmable device vendors
- OTP PROMs can not be easily programmed in
- Custom methods of using a FLASH and CPLD require additional
support and engineering for instance to enable the FLASH to be
updated in-the-field. It is riskier as many companies have already
reported bringing their system down because the FLASH got
improperly re-programmed and the FPGAs needed to program the FLASH
a second time were not properly configured.
- FLASH and CPLD method of programming is inflexible and doesn't
support decision making necessary for creating flexible systems
that adapt for customer specific needs. Data is loaded into
the FPGA in a 'blind' sequence, even potential
disasterous failures during the programmed are ignored by the CPLD
- FLASH is unprotected and FPGA binaries are easily examined and
possibly reverse engineered. Programming methods using
CompactFLASH are even more vulnerable since the CompactFLASH can be removed and easily duplicated.
- PROMs only program FPGAs and do not
re-configuring a non-volatile CPLD in the system
Embedded Configuration Solution
The ideal solution provides the design engineer with a scalable and reusable methodology that supports centralized anytime/anywhere re-configuration of an entire system.
To implement this methodology Intellitech provides the TEST-IPTM family of patent-pending Infrastructure Intellectual Property (IP) modules.
FPGA Programming and Test processor
SystemBIST eliminates the need for PROMs and other 'home-brewed' in-system configuration techniques for designs that employ multiple FPGA/CPLD devices.
- The SystemBIST Embedded Configuration and Test Processor can deliver up to 15 different pre-programmed FPGA designs without PROMs. SYSTEMBIST costs approximately $60.00 per board compared to a typical PCB with three high-density FPGAs requires over $200 in re-configurable PROM parts cost and the PROM circuitry could use 2.25 square inches of PCB area
- SystemBIST is vendor independent and
programs any IEEE 1532 or IEEE 1149.1 compliant programmable
- SystemBIST is a processor that can make decisions and load
partial designs into the FPGA on the fly reducing the FPGA size to hold all of the designs simultaneously
- SystemBIST replaces OTP PROMs and can re-configure the system in the field an unlimited number of times
- SystemBIST is a standard reusable IP
solution based on IEEE 1149.1
- SystemBIST is integrated with the external Eclipse test
development and verification tool. All Eclipse tests,
scripts and FPGA configuration can be pre-verified, automatically
downloaded to SystemBIST and guaranteed to be operational without
a second step of embedded debug.
Intellitech's SystemBISTTM Embedded Configuration and Test Processor enables device configuration suites to be developed, validated, and embedded directly into the system. System re-configuration can take place anywhere so that engineering changes could be easily made at any point in time during a product's life cycle. Manufacturing tests are also embedded into this system eliminating the need to run digital tests using ICT. Embedded test also permits the same set of tests to be used in lab prototyping, volume PCB manufacturing, System Integration, HALT/HASS tests, at customer power-up, field service and depot repair.
A complementary IP module FAC performs in-system FLASH programming. FAC achieves its fast on-board programming times by using advanced data de-serialization and protocol optimization algorithms to minimize the number of scan operations and data required during FLASH programming. This enables the FAC to program FLASH devices in-system at speeds equivalent to off-board programming. The FLASH memory protocols of the FAC are fully configurable in-system, using Intellitech's Eclipse family of 1149.1 based tools allow it to support a wide variety of FLASH memory devices and protocols from vendors such as Intel and AMD.