Silicon Debug - NEBULA Silicon Debugger
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Silicon Debug is easy with the NEBULA Silicon Debugger - a full DFT focused tester. NEBULA is a silicon debug and validation platform that is
remotely accessible over the network. Unlike full pin-access testers, NEBULA enables 'in-situ' silicon debug, a term coined by Intellitech. It enables engineers to accelerate the
silicon debug of prototype IC designs, resulting in faster time-to-volume. The NEBULA Silicon Debugger provides advanced features for performing early validation of
DFT infrastructure and test patterns, and to debug and diagnose problems in first
silicon. The NEBULAsolution supports test pattern formats from leading ATPG Tools, such as Synopsys' TetraMAX, Mentor Graphics FastScan and Cadence's Encounter Test (formerly
IBM TestBench), and they can be imported without translation to NEBULA.
With the remote
network access capabilities of the NEBULA platform, design and test engineers
can have debug and test access to first silicon from their office, or from any remote
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Silicon Debug - A Structured Solution
With increased circuit complexity and advanced packaging, silicon debug is
becoming more difficult. Physical access and visibility into the design for debug
are significantly reduced, especially during prototyping when the silicon is in-system.
As a result, these designs call for structured debug methods that validate
tests that later can also be used by production testers. The NEBULA Silicon
Debugger platform was designed for use with these advanced structural test, at-speed test and
diagnosis methods.
Where are all the tester pins? Structural stuck-at and path-delay tests do not need
high-speed access to the pins of an IC as functional test does. NEBULA - a full DFT Focused Tester - takes
advantage of this DFT and performs the same tests with a reduced number of
pins. NEBULA can do what other testers can't do - 'in-situ' validation and fault finding while the IC is in the target system - critical for identifying real world problems. How will my tester patterns work on NEBULA? Even though the production test patterns may have full physical access,
NEBULA provides 'virtual access' and enables interactive correction of these
broadside test patterns without translation test vectors and scan-chains.
Scan-Chain ordering changed? No problem - scripts written with NEBULA can be used from one revision of a device to the next without being re-written.
Validate DFT with Proven Flows
NEBULA can be used to quickly validate DFT infrastructures
such as internal scan, IEEE 1149.1 Boundary Scan, memory BIST and logic BIST.
It enables BIST and ATPG patterns, such as for stuck-at and path-delay faults, to
be validated by design and test engineers. With NEBULA, engineers
can perform validation as soon as the first ICs are available, eliminating the dependency on
the limited availability of high-cost ATE resources.
Benefits
- Provides a solution for
complex designs with advanced
packaging, where physical access
is limited and structured test methods are needed.
- Start validation as soon as first article devices are available. Use to test and diagnosis first IC, and to perform structural characterization. Eliminates the need for high-cost ATE during the prototype bring-up phase.
- With proven flows, easily import
vectors from Synopsys TetraMAX
and Cadence TestBench. No
translations or modifications are
needed.
- Integrated support for TetraMAX
diagnostics to pinpoint IC
failures to the gate and net level.
- Quickly and easily validate DFT
infrastructure, and production test
patterns. Accelerates time-to-volume by pinpointing design problems early in prototypes
- Provides ' in-situ' access to
prototype ICs for
functional based failure identification, where the IC is
on a board or in the system.
- Enables validation of production test
patterns in a 'in-situ' or reduced pin
contact environment without test
pattern translation
- Re-useable test and validation scripts
throughout the design hierarchy,
revisions and within
different test environments - saves
time and reduces development
costs.
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