Intellitech's NEBULA Speeds
Silicon Debug for Synopsys' TetraMAX Users
Network Based Platform Provides
Simplified Flow From ATPG to Desktop DFT Validation, Silicon Debug
and Diagnosis
DURHAM, N.H.--(BUSINESS WIRE)--Sept. 8,
2003--Intellitech Corporation, the technology leader in
scan-based configuration, debug and test solutions today
announced the availability of the NEBULA Silicon Debugger(TM).
The NEBULA speeds test vector debug time from weeks to less than
a half of a day through its direct knowledge of on chip
Design-for-Test structures and integrated use of
Synopsys TetraMAX(R) ATPG patterns and diagnostics. The NEBULA
enables remote testing of prototype silicon for stuck-at faults,
path-delay faults, at-speed BIST and in-situ functional debug.
Failures can be quickly isolated to the gate and net level with
the integrated access to the TetraMAX fault-simulation database
for lookup of ATPG faults. The NEBULA acronym is loosely
translated as Network Based debug and Logic Analysis since the
debug and validation platform is remotely accessible by design
and test engineers over a wide area network.
With increased circuit complexity and advanced packaging (at
both the chip and system levels) silicon debug has become more
difficult and more time consuming. Physical access and visibility
into the design during debug is significantly reduced, making
traditional unstructured debug methods less productive. A recent
study by Gartner Dataquest indicates that the design time of a
large ASIC takes between nine and 12 months. In the same study,
it was shown that the typical silicon debug time is about
two-thirds that. While it has always been obvious to try to
shrink the design cycle to achieve time-to-volume gains, it has
been less obvious that similar gains in time-to-volume can be
achieved by shrinking the silicon debug times.
"Silicon debug continues to be a growing segment of the test
and validation market," said CJ Clark, Intellitech's chief
executive officer. "We helped pioneer silicon debug back in 1996
with our first generation product, the RCT platform. NEBULA will
help designers to meet critical time-to-volume windows by
enabling early structural test, vector validation, IC
characterization, gate level failure analysis, in addition to
enabling full-speed functional debug." Key to
shortening the silicon debug cycle is the 'smart
tester' architecture of NEBULA. It understands the difference
between serial scan test data and parallel pin test data allowing
the engineer to debug using functional elements of the design
rather than counting 'bits' from tester channel results. The
architecture and scripting language enables complex
decision-making during execution of test programs that is not
possible with memory-behind-pin tester architectures. For
instance, NEBULA can apply test patterns and based on the failure
that occurs, program an on-chip non-volatile memory with data to
disable the faulty area and enable a redundant logic area. The
NEBULA platform also understands the DFT infrastructure inserted
by Synopsys tools, which is a departure from
traditional memory-behind-pin DFT focused platforms and 'big
iron' ATE. The NEBULA Silicon Debugger takes advantage of the DFT
infrastructures such as internal muxed flip-flop scan, IEEE
1149.1 or LSSD inserted by Synopsys DFT Compiler and BSD
Compiler. The direct knowledge of the test structures inserted by
these DFT tools plus an understanding of how to interpret the
ATPG patterns generated by TetraMAX reduces many of the variables
confronting the engineer during first silicon debug. The NEBULA
also incorporates a special "Test Diagnostics Server"
which enables bidirectional communication with a user's TetraMAX
diagnostics license. This enables gate and net level diagnostics
for TetraMAX based tests running on remote NEBULAs and windows
based PCs. NEBULA is the result of Intellitech's membership in
Synopsys' in-Sync(R) interoperability program, through which
Synopsys works with tool providers to maximize the productivity
of mutual customers.
In-situ Debug
The NEBULA Silicon Debugger interfaces to an
IC using standard test protocols, such as muxed scan, LSSD (Level
Sensitive Scan Design) or IEEE Std. 1149.1. The NEBULA Silicon
Debugger uses a very low pin count access method that enables
in-situ access to prototype silicon, that is, the IC can be on a
PCB or in the system while debug is performed. Even though test
patterns are developed for production tests with full pin
contact, NEBULA will interpret and exercise the patterns
differently for the in-situ environment without
vector translation. In-situ debug is especially useful since
custom DUT cards are not needed, and debug can be performed on
early FCS and prototype parts without the removal of the silicon
from the PCB. This is a major departure from traditional low-cost
DFT focused debug platforms, which require full pin access and
cannot support the re-use of test patterns and debug scripts
throughout the design hierarchy. Time and development costs can
be reduced since design engineers can re-use test patterns and
scripts in various different debug and
validation environments. The NEBULA Silicon
Debugger platform provides built-in software support for external
instruments, such as power supplies, frequency generators, RF
signal generators and thermal chambers, that are needed for test,
debug and characterization. Industry standard instrumentation,
such as PXI, VXI and GPIB instruments, are readily supported
through the VISA (Virtual Instrumentation Software Architecture)
and IEEE-488 Instrument interfaces. These instruments can be
controlled with the built-in capabilities of NEBULA,
which provide scripting and interactive GUIs, or alternately
through user defined scripts and GUIs. VISA support provides an
'open architecture' for users to add instruments and digital I/O
as they need. It enables the NEBULA Silicon Debugger platform to
provide broad plug and play capabilities, allowing design and
test engineers to develop interoperable, multi-vendor, solutions
that are reusable from project to project. More information can
be found at http://www.silicondebug.com/products/silicondebug.asp
Pricing and Availability
The NEBULA Silicon Debugger is available now
from stock, starting at approximately $50K for desktop hardware
and a floating license. Contact Intellitech at http://www.intellitech.com for
various options.
Intellitech is a registered trademark of
Intellitech Corp. NEBULA Silicon Debugger is a trademark of
Intellitech Corp. Synopsys, TetraMAX and in-Sync are registered
trademarks of Synopsys, Inc. DFT Compiler is a trademark of
Synopsys, Inc. All other trademarks or registered trademarks
mentioned in this release are the intellectual property of their
respective owners.
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CONTACT: Intellitech
Corporation
Kareen Lefoley, 603-868-7116 x106
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