Internal JTAG
New to P1687? IEEE
P1687/IJTAG - The scope of this standard is to develop
a methodology for access to embedded test and debug features
via the IEEE 1149.1 Test Access Port (TAP). IEEE P1687 is
sometimes referred to as IJTAG, or Internal JTAG however 1149.1
has always had internal TDRs part of the standard. The official
website is here P1687 Website
although it is somewhat outdated. These embedded test and debug
features are referred to as 'instruments'. The purpose of the
instruments is not just for on-chip test but also the on-chip
instruments can facilitate board and system level test. A short
list of example instruments would be: on-chip process monitors,
temperature monitors, PLLBIST, Memory BIST and SERDES BIST. In
the last year, the working group has made significant progress
in deciding on key languages and hardware architectures. See
Intellitech's presentation to the WG in 2008 - Intellitech
IJTAG.
This paper was presented at NATW: IJTAG Basics. Much of the language syntax of ICL (Instrument Connectivity Language) has changed as of 2011.
P1687 proposes to use PDL (with somewhat less features than 1149.1-2013) and ICL (instead of BSDL). An example ICL is as follows:
Module (block1) {
Ports {
si1 { Function: ScanIn; }
so1 { Function: ScanOut;
Source: TDR1[0]; }
en1 { Function: Select; }
se { Function: ShiftEn; }
ce { Function: CaptureEn; }
ue { Function: UpdateEn; }
tck { Function: TCK; }
}
ShiftRegisters {
TDR1[63:0] {
CaptureSource : 32'b0,RX_M;
}
}
Alias RE = TDR1[63] { iApplyEndState 1’b0; }
DataRegisters {
R0[31:0] { WriteEnSource : R0_W
WriteDataSource : TDR1[31:0]; }
R1[31:0] { WriteEnSource : R1_W;
WriteDataSource : TDR1[31:0]; }
R2[31:0] { WriteEnSource : R2_W;
WriteDataSource : TDR1[31:0]; }
R0_0[7:0] { WriteEnSource : R0_0_W;
WriteDataSource : R0[7:0]; }
R0_1[7:0] { WriteEnSource : R0_1_W;
WriteDataSource : R0[7:0]; }
R0_2[7:0] { WriteEnSource : R0_2_W;
WriteDataSource : R0[7:0]; }
R1_0[7:0] { WriteEnSource : R1_0_W;
WriteDataSource : R0[7:0]; }
}
LogicSignals {
R0_W : Select { TDR1[63:62],TDR1[61:32] == 32'b10000000000000000000000000000000; }
R1_W : Select { TDR1[63:62],TDR1[61:32] == 32'b10000000000000000000000000000001; }
R2_W : Select { TDR1[63:62],TDR1[61:32] == 32'b10000000000000000000000000000010; }
RX_M[31:0] : Case TDR1[63:62],TDR1[5:0] {
8'b01000000 : 24’b0,R0_X_M[7:0];
8'b01000001 : 24’b0,R1_X_M[7:0];
8'b01000010 : 24’b0,R2_X_M[7:0];
}
R0_0_W : Select {R0[31:30],R0[29:24] == 8'b10000000; }
R0_0_W : Select {R0[31:30],R0[29:24] == 8'b10000001; }
R0_0_W : Select {R0[31:30],R0[29:24] == 8'b10000010; }
R0_X_M[31:0] : Case R0[31:30],R0[29:24] {
8'b01000000 : R0_0[7:0];
8'b01000001 : R0_1[7:0];
8'b01000010 : R0_2[7:0];
}
}
}
New to IEEE P1687?
You can read more about it in the P1687
whitepaper (2010): IJTAG/P1687 whitepaper
Presentation to P1687 WG (October 6, 2010) Addressable Instruments
Presentation to P1687 WG (2008) - Intellitech
IJTAG
As our work in the ICL tiger team progresses, the NEBULA software will be updated and documentation will explain the full syntax and semantics of the language.
In order to download your free copy of the NEBULA client,
Xilinx USB Cableserver and ISIS, you must register on the
website here: Register.
|
