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IJTAG/P1687 Software for Instrument Development

New to IJTAG/P1687? You can read more about it in the P1687/IJTAG whitepaper: IJTAG/P1687 whitepaper

Overview

P1687/IJTAG re-usees the basic concepts that Intellitech pioneered in the 1990s. This architecture compiles 1149.1 BSDL, BSDL extensions with mnemonics and internal scan registers into a database and accessing those on-chip registers using JTAG extensions to TCL. TCL or Tool Command language is an open source language see www.tcl.tk. This capability was introduced in 1997 and became the basis for Intellitech's NEBULA Silicon Debugger (NEBULA Silicon Debugger) and other products. The TCL language with extensions enables scripts to be written that enable write and reads to internal scan registers and on-chip DFx structures via the JTAG TAP. The major advantage of the approach is that the scripts are re-targetable - there is no scan-chain shift information present like WGL or STIL ATE vector languages.

Screen shot of NEBULA running with Synopsys VCS
You can Register for a free copy

IEEE P1687/IJTAG - The scope of this standard is to develop a methodology for access to embedded test and debug features via the IEEE 1149.1 Test Access Port (TAP). IEEE P1687 is sometimes referred to as IJTAG, or Internal JTAG. The official website is here P1687 Website although it is somewhat outdated. These embedded test and debug features are referred to as 'instruments'. The purpose of the instruments is not just for on-chip test but also the on-chip instruments can facilitate board and system level test. A short list of example instruments would be: on-chip process monitors, temperature monitors, PLLBIST, Memory BIST and SERDES BIST. In the last year, the working group has made significant progress in deciding on key languages and hardware architectures. See Intellitech's presentation to the WG in 2008 - Intellitech IJTAG.

We are pleased that Intellitech's input has helped the upcoming IEEE P1687 standard move in the direction of using TCL and a database of instrument connectivity. The Working Group has voted to use TCL (pronounced 'tikel') with extensions to write and read on-chip Instrument registers. The WG has also decided on a language describing the connectivity of the instrument registers called ICL (pronounced 'ickel') Instrument Connectivity Language. ICL has many of the constructs like Intellitech's BSDL extensions for internal scan such as Mnemonics and bus definitions. Our experience with IEEE 1149.1 indicates that freely accessible tools for the community will help promote and move the IEEE standard forward to wider acceptance. There is still work to do within the P1687 working group and probably some time before automation of instrument insertion and connection is delivered in the EDA industry. In the mean time, much can be gained with using JTAG internal scan access and creating test benches in TCL against the simulation of the IC, Instrument and/or SoC.

# set the scope
iScope TOP.i_tb0

iWrite addr 0x201
iWrite data 1
iWrite wb 0
iApply
iRead q
iApply
if {[iGetReadValue q ]==1]} {
puts “ERROR in Write setup reg 0x201”
}

Example re-targetable TCL with internal register access

Where ICL and TCL are used

Free software

The NEBULA software for IJTAG/P1687 is free, however, in order to communicate with a physical IC TAP, you will need to purchase a Xilinx USB Platform Cable I or II, if you do not have one already. Purchase Xilinx Cable I or Cable II. To simulate your IC or on-chip instrument, you will also need Synopsys's VCS simulator to connect the tools to the simulation environment. VCS is a product of Synopsys and is sold separately.

Operational Overview


First stage - Develop the TCL/PDL driver for the Instrument stand-alone in the simulation environment	Second stage - Simulate instrument with TCL/PDL driver along with other Instruments at the IC level
Intellitech pioneered the development of JTAG over TCP/IP in the late 1990s - separating the client JTAG software from the target hardware via TCP/IP. This TCP/IP packet architecture is used to enable NEBULA to connect to simulation servers on separate hosts or to connect to JTAG pods such as the Xilinx USB pod. NEBULA supports TCL instrument driver development in multiple stages. At the simulation level of the Instrument. Develop TCL drivers which are re-used during each phase of verification and use. Stage 4 (not shown) is to re-use the instrument and TCL driver at the PCB level JTAG.
		Stage 3 - Verify Instrument and Instrument TCL driver in silicon with other instruments at the IC level

Frequently asked questions:

What's different between using 1149.1 with on-chip internal register access and P1687?

The major advantage of P1687 is that an instrument provider may provide an instrument independent of the design of the IC's internal scan-chains and network of instruments. The Instrument provider can create a description of the operation of the instrument in a standard language (TCL) and not be concerned where the instrument is in the scan-chain. While this has been a basic capability in Intellitech's tools for some time, P1687 standardizes on the TCL language and syntax. P1687/IJTAG instrument drivers do not support instruction register commands of the IC TAP, this enables the instrument driver to be developed independent of where the instrument will be used. P1687/IJTAG adds the capability of describing addressable instruments, where a single TDR may interface to multiple instruments. . P1687 compliant software will manage the mapping of the registers of the instrument driver in TCL with the P1687 scan-chains (network).

What's included in the free download?

Windows NEBULA TCP/IP Client software with base features of:

BSDL database compiler with Intellitech extensions for internal scan and P1687
TCL/TK interpreter with extensions for P1687 and for basic JTAG - apply and single step
SVF support - Record and Apply SVF, single step
WGL Support - Record WGL patterns and Apply WGL patterns from Synopsys TetraMAX

iSIS Intellitech Simulation Interface Server - for VCS on Redhat Linux 64 bit

iCableServerX - Intellitech's Window's based cable server for Xilinx USB pod.

Alarm Clock example files - Source and synthesized Verilog with Internal Scan inserted by TetraMAX, BSDL and BSDL extensions, Mnemonic support, TCL example files, Makefiles for use with VCS on Linux.

Coming as the P1687 WG progresses

P1687 Compliant Compiler for the ICL (Instrument Connectivity Language)
Linux based Test Diagnostic Server for TetraMAX. This diagnostic server enables remote execution of TetraMAX for diagnostics from a Windows based Client.

Future:

iCableServerX for 64 bit Linux. This is a Linux version of the Intellitech Cable Server for the Xilinx USB pod.
64 bit RedHat Linux based NEBULA Client
STIL pattern recording support
Additional Simulator support. (Let us know via email if you have a preference)

Why is this Free? Is there a catch?

There is no catch. Free tools will enable the upcoming IEEE P1687 standard to have wide-spread adoption. Free versions of NEBULA will enable leading companies to do real productive work with JTAG based access to on-chip scan-chains and at the same time enable Universities and research institutions to perform useful research in the area of on-chip JTAG DFx and Instrument register access. Users will be able to validate the instrument drivers written in TCL against the simulation of the instrument and then against the actual hardware. With free software the community will have a common platform to validate instrument drivers and develop unique instruments - that can be validated pre-silicon and used for silicon bring-up.

Intellitech benefits as more ecosystem is developed to increase fault coverage for embedded JTAG test. Intellitech has educated the industry for over ten years on how to reduce functional test development by embedding access to on-chip JTAG test features with Intlelitech's SystemBIST IC. JAF Test, JTAG Assisted Functional Test, breaks the system functional test challenge down into smaller manageable parts. Test development can be done with just an understanding of the micro-parts, how to execute a PRBS test over a serial link for example, without the developer needing to know the entire mission mode functionality of the system.

Intellitech may offer additional free opportunities or charge token fees of US$100 to US$400 for a floating license in the future. A very small fee for a tool in this class. Some advanced features such as the schematic viewer have a temporary license only. A full license for this feature is available for $1500.00. Each year Intellitech may ask you to re-validate your email address.

Is "free" a sustainable business model?

Intellitech's primary revenue is not from NEBULA but from our components, IP, patents, methodologies and high-end testers. There are many quality free software packages today from FPGA vendors for instance. Many segments of the industry are also using forms of free software. DimDim web conferencing is a good example. As the use of the standard matures and new capabilities emerge, there will possibly be features of NEBULA that we reserve the right to charge for. You may choose not to purchase those features. Support is not included with the free software. Documentation on how to install and operate the software is provided. If this is not sufficient you will need to purchase a support package at $595 for a five (5) hour block of support time.

In order to download your free copy of the NEBULA client, Xilinx USB CableServer, and ISIS, you must register on the website here: Register.

What can I do with this now, prior to getting a working draft of the rules of IEEE P1687/IJTAG ?

The software will allow you to describe internal scan-chains which are accessible via JTAG and import them into BSDL with Intellitech extensions. You can simulate your design in VCS and connect to the JTAG of your design in simulation to validate TCL scripts with JTAG register access. When the actual IC is available, you can use a low cost Xilinx USB pod ($250 sold by Xilinx) to access the on-chip JTAG accessible registers. If you have TetraMAX you can generate ATPG patterns to apply via JTAG and get diagnostics from TetraMAX. You can also write generic TCL scripts which you can record as WGL ATE tester patterns..

In order to download your free copy of the NEBULA client, Xilinx USB Cableserver and ISIS, you must register on the website here: Register.

TetraMAX and VCS are registered trademarks of Synopsys