Six shipments of Intellitech’s SRL with Electronic Chip ID shipped in Q1
Our newest Scan Ring Linker now includes a free software utility which enables Xilinx Impact and Chip-scope users the ability to control the scan-chains on-the-fly.   You can read more about Electronic Chip IDs -  Anti-Cloning with security ID
Intellitech Headquarters moves to expanded 5,000 Sq. ft. facility in Dover, NH
Our TEST-IP family of components, our success with the PT100Pro Tester and you our valued customer have helped us grow.  Intellitech’s new address is 69 Venture Drive, Dover, NH 03820.  Our new telephone number after May 1st will be 603-750-7116.   Please note the change from 868 to 750.  There may be some telephone or website interruptions the 24th.-25th.  Intellitech New Address
Upcoming Events
NATW 2010, Hopewell Jct, NY, May 12th
Panel-   Intellectual Property: Publish, Patent, or Trade Secret?
Paper-   Basics of  IEEE P1687 – Understanding this enhancement to 1149.1
HOST Hardware-Oriented Security and Trust June 13-14, 2010 Anaheim, CA
Papers/Events you may have missed
VLSI Test Symposium 2010, Santa Cruz, April 19th-21st
“iMajik:  Making 1149.1 TAPs disappear and reappear in SoCs and 3D packages”
Updates to IEEE 1149.1-2010 April 21st  3PM  Peninsula Room
Updates to IEEE P1687  April 21st  4PM  Peninsula Room
DATE 2010  Dresden, Germany
"The Impact of Nanometer Technologies on Manufacturability on Yield"
CEO CJ Clark  invited speaker at DATE executive panel.
Updates to IEEE 1149.1-2010 March 8th
Updates to IEEE P1687  March 8th
3D IC TTSC Study Group
Managing multiple TAPs in 3D packages
New Free Software Tools
BSDL Syntax Checker
Our BSDL Syntax checker is on the web.  If you need to check for compliance to IEEE 1149.1 or just need better diagnostic information when your BSDL doesn’t compile, try it out.  BSDL Syntax Check
NEBULA for Internal JTAG
     Do you need to validate JTAG TAP-based DFT prior to tape-out?   Interested in getting started with IJTAG (P1687) before it becomes a standard?  Our NEBULA software is now available for free.  NEBULA will allow you to perform verification of your instrument and on-chip DFT by driving the JTAG TAP in Synopsys VCS® and using high level TCL language to script the verification flow.   We’re teaching the industry the right approach, rather than using Verilog test benches to drive simulation.  The Verilog test benches cannot be used with the actual silicon and does not validate the BSDL or ICL description language files.  Our approach with BSDL, P1687 ICL and TCL enhanced with JTAG commands is the best way for controlling on-chip infrastructure-IP.    This basic approach of compiling scan-information into a database and then operating on it via TCL commands has been adopted by the IEEE P1687 working group.   (For serious users developing ICs only. This software requires a Synopsys VCS® license and is not suitable for PCB test.)
New Eclipse/Scanexecutive software releases coming in May. 
Release includes support for local and remote Xilinx USB Pods.
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