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July 15, 2010 Meet with Intellitech representatives at SemiconWest 2010 and ATE Vision 2020 Workshop, San Francisco, CA June 14-16, 2010 Meet with Intellitech representatives at DAC 2010, Anaheim, CA. June 14, 2010, "Challenges in inserting Trojans - Indie, They're digging in the wrong place!", HOST Symposium, Anaheim, CA. Trojan Circuits in ICs/FPGAs June 13, 2010, "IJTAG Basics", DAC SoC Debug Workshop, Anaheim, CA. IJTAG/P1687 June 13, 2010 "Anti-tamper JTAG TAP design enables DRM to JTAG registers and P1687 on-chip instruments" HOST 2010, Anaheim, CA. Anti-Tamper JTAG TAP May 14, 2010 Introduction to IEEE P1687/IJTAG, CJ Clark, Bill Tuthill, NATW, Hopewell, JCT NY. IJTAG May 12, 2010 Intellectual Property Panel Session, "Patents a tool for engineers". NATW, Hopewell, JCT NY. April 21st, 2010 Informational meetings on IEEE 1149.1-2010 (JTAG) and IEEE P1687 (IJTAG) to be presented by Intellitech at VTS 2010 Santa Cruz, CA April 20th, 2010 "iMajik: Making 1149.1 TAPs disappear and reappear in SoCs and 3D packages", VLSI Test Symposium, Santa Cruz. TAPs for 3D/Multi-Core April 16th, 2010 Intellitech to move to new expanded headquarters, May 1st. New Address: 69 Venture Drive, Dover, NH 03820 March 9th, 2010 "The Impact of Nanometer Technologies on Manufacturability on Yield", CEO CJ Clark is invited speaker at DATE executive panel. Yield February 24th, 2010 Informational meetings on IEEE 1149.1-2010 (JTAG) and IEEE P1687 (IJTAG) to be presented by Intellitech at DATE 2010 in Dresden, Germany, March 8th. 1149.1 and P1687 September 9th, 2009 "Wireless JTAG BOST approach to lowering production JTAG costs" and “Micropin Vertical fixtures for volume PCB test” to be presented by Intellitech at the Board Test Worksop 2009, September 16 and 17th in Ft. Collins, CO August 31th, 2009 Interview with customer Jake Haddock, CTO of Alta Data Techologies. JTAG Success August 26th, 2009 Meet with Intellitech at FPGA Camp at Juniper Networks in Sunnyvale, CA. Invited speaker CJ Clark presents "Validating FPGA SERDES throughout the product lifecycle". FPGA Camp August 25th, 2009 The benefits of SystemBIST FPGA configuration is highlighted in the article "Managing Multiple Bitstream Images..." by Neil Jacobson in Chip Design.. Bitstreams August 23rd, 2009 Intellitech's BSDL Syntax Checker is now available for free semantic, grammar and IEEE 1149.x rule checks. Free BSDL Syntax Check August 17th, 2009 "Intellitech’s CEO, CJ Clark is invited judge for New York University’s Cyber Security Awareness Week, October 12th ” Anti-tamper Awareness August 10-11, 2009- Meet Intellitech at Command, Control, Computers, Communication, Intelligence, and Information Summit (C4I2), at the Taj Palace, New Delhi, India. C4I2 Register for the white paper: New Strategies for cost effective production PCB test and configuration This requires Chinese fonts:
“I like the fact that Intellitech has good overall long
term vision for IEEE 1149.x based test. They are not just reacting
to what I need at the moment....Support has been one of the best
I’ve ever encountered from a vendor...We truly feel that
Intellitech helps us deliver a better product to our
customers..." Jake Haddock CTO Alta Data Technologies We had boards that had ‘passed’
ICT and boundary-scan tests at the CM, but were non-functional.
Intellitech’s innovative multi-processor fault coverage
covered interconnects missed by the CM’s tests. Joe Gagnier, Manager, Unisys
“We’re using Intellitech’s
PT100Pro with FlashJETT in our production to program two different
microcontrollers on four PCBs at a time. It is no longer
business as usual in the auto industry. We must use new
solutions which provide the most value for our budget.
Intellitech’s FlashJETT solution enables us to achieve
production line throughput while simultaneously meeting our cost
objectives” Nagabhushana Shastry SMT Manager Continental
Automotive Components
"We chose Intellitech's PT100 PCB tester because it enables us to program and test many PCB cards concurrently. The PT100 enables us to expand the number of tet channels as our production needs grow, protecting our investment for many years to come. Concurrent test lowers our overall cost of test and FLASH programming when compared to ICT." Marcus Andrade, CEO, VTEC "In our market, system cost is an important factor in our customer's decision process. Xalted selected Intellitech's SystemBIST and Concurrent JTAG Architecture in order to lower our FPGA configuration and system test costs." Robert D. Connolly V.P. Product Engineering, Xalted Networks (India) |
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