Come see how you can lower your costs with solutions from Intellitech Corp.     

Join us at the International Test Conference, Booth 318 for demonstrations on Intellitech’s solutions for Silicon Debug, PCB self-test and Volume PCB test.  Intellitech’s unique approach to Design-for-Test, Design-for-Debug and Design-for-Configuration enables your company to lower product costs.  You’ll learn how to save your company money and get a chance to win an Apple iPod!


Need to find out the latest in test, debug and configuration technology?  Come interact with industry experts Dr. Bernd Koenemann and CJ Clark at the following free tutorials for customers and potential users. Please go to to read their bios, register and find out more.   Tutorials to be given at the Hyatt Regency, Santa Clara, CA, Alameda Room Monday-Wed October 23-25, 2006.




8:15a - 9:00a

GPIB/PXI test w/ 1149.1 and Eclipse

9:30a - 10:15a

Using PCB EDIF for fast-accurate ATPG


Linking multiple scan-chains on PCBs

1:00p - 2:00p

Concurrent JTAG - concurrent test for 1149.1

2:15p - 3:15p

SystemBIST - PCB self-test in minutes

3:30p - 4:15p

DFT for TAP based functional/vector debug



10:30a - 11:00a

PCB Test Myth Busters

11:10a - 12:00p

At-speed SERDES/DDR Test with 1149.1

4:00p - 4:45p

System level 1149.1 solutions

5:00p - 5:45p

How to achieve zero digital test time.



1:45p - 2:30p

Is boundary-scan on ICT the right solution for you?

2:45p - 3:30p

Test Engineers - show PCB designers new


ways for FPGA configuration and get JTAG


self-test for you.





What you’ll see at Intellitech’s ITC booth


Flexible FPGA Configuration device with JTAG self-test


Expecting more for the money you’re spending on FPGA proms and platform Flash?  Intellitech’s FPGA configuration device, called SystemBIST, can get you to market faster with in-the-field upgrades and comprehensive PCB self-test.  SystemBIST enables decision-based FPGA programming, ‘failsafe’ FPGA updates and PCB level JTAG self-test – something a configuration prom just can’t do.  SystemBIST’s patented capability enables your company to eliminate returned PCBs with No Fault Found (NFF).

Check out the new ready-to-run evaluation PCB.  Use it to design SystemBIST into your next PCB or use it as a PC-less low-cost JTAG tester! SystemBIST.


At-speed SERDES and DDR testing with JTAG!


Intellitech’s Eclipse family of PCB Test, FPGA configuration and FLASH programming tools now support at-speed testing of Xilinx Virtex4 Rocket I/O and DDR2 memories.  Functional tests not pinpointing the problems for you?   Get plug-n-play at-speed BERT tests for SERDES connections and DDR with robust diagnostics and without the headaches. 


In-Situ Silicon Debug


Intellitech's NEBULA Silicon Debugger gives you visibility into your silicon during the critical bring-up phase.  NEBULA’s integrated net and gate level diagnostics for TetraMAX and Encounter Test reduces the amount of time spent debugging SoC and IC test vectors from weeks to less than a day.  Using Intellitech’s reduced pin strategy; these IC tests can also be executed in the field with SystemBIST (above).

Once structural tests have been validated, begin functional debug with NEBULA’s scan-chain dump capability.  Dump scan-chain and memory data after critical events and failures.  The scan-chain information and internal memory data is then brought into the simulator, effectively saving millions of clock cycles of simulation.  NEBULA Silicon Debugger


Run ASSET InterTech ScanWorks® tests and diagnostics with Eclipse


Eclipse now supports execution of ASSET InterTech ScanWorks® based tests and diagnostics.  Develop your tests in ScanWorks® and apply with Intellitech’s PT100, UltraTAP or SystemBIST.  Eclipse will detect the failures and pass this information into ScanWorks® for creating the diagnostics.   Find out more about other features for design visibility, interconnect testing, memory testing and on-board FLASH programming.


PT100 Demonstrations


Need a scalable test solution? Learn more about how the PT100 tester with concurrent JTAG can optimize your production line – testing PCBs, MCMs or ICs as fast as you can handle them.   The PT100 enables you to easily calculate your throughput as a function of handling time and not test time.  With the PT100, testing with JTAG is never slow!




Copyright © 2006 Intellitech Corp. All Rights Reserved.  TetraMAX® is a registered trademark of Synopsys. Encounter® is a registered trademark of Cadence. ScanWorks® is a registered trademark of Asset-Intertech