Durham,
NH - (BUSINESS WIRE) - December 1, 2003. - Intellitech Corporation,
the technology leader in scan-based configuration, debug and test
solutions today announced the availability of the PTC, an
addressable 1149.1 gateway device. The PTC IC is designed into
what is called 'blade' PCBs, boards designed to plug into a
multi-slot or multi-cabled backplane. It provides the
infrastructure necessary for multi-PCB FPGA configuration and system
PCB to PCB interconnect test.
It is a key element in designing multi-PCB systems that can
perform in-the-field upgrades to all of the non-volatile devices of
the system. It's also a
necessary element for performing tests of PCB to PCB gigabit SERDES
and LVDS connections and diagnosing connection problems to the
pin. It can be used on blades targeted
for proprietary telecomm backplanes or on PCBs used in standard
backplanes such as cPCI, VME and VXI.
The PTC, for Parallel Test
& Configuration, is the industry's only gateway device for
1149.1 test and configuration of multi-board systems that can scale
with the size of the system.
The PTC's patent-pending parallel test capabilities using
IEEE 1149.1 enable simultaneous test and on-board programming of all
similar PCBs in a system.
This
enables manufacturing PCB tests to be re-used at the system level,
during integration and burn-in without incurring test time
penalties."Previous addressable
multi-drop 1149.1 architectures lacked scalability. If the test time for one PCB
in the system was 45 seconds, then 10 similar PCBs resulted in 450
seconds. Each PCB had
to be tested one at a time.
With Intellitech's patent-pending technology, the time to
test those 10 PCBs would only be 45 seconds", said Mike Ricchetti,
Intellitech's Chief Technology Officer. "It is particularly useful
in that FPGAs and other programmable devices can be configured and
verified simultaneously.
It is not necessary to
individually interrogate each device on each PCB to see if they were
programmed successfully."
IEEE 1532, the in-system
configuration standard, has become the preferred method of
programming devices such as CPLDs and FPGAs. The PTC shortens the
design time for creating a multi-PCB IEEE 1532 compliant bus
throughout the system.
With parallel FPGA configuration, the PTC can achieve higher
FPGA configuration data rates than proprietary methods, with less
design time and lower parts cost. For example, FPGAs are
configured at power-up using the FPGA vendor's proprietary 8 bit
wide interface. The
proprietary interface supports programming the FPGA at data rates
from 1mb/sec to 152Mb/sec, with 80Mb/sec typical. However, this proprietary
interface must be local to each FPGA, requiring configuration
resources on each PCB in the system, increasing the parts cost. Using a 20Mhz test clock and
the PTC architecture, 4 PCBs can be configured from a single
programming resource simultaneously, providing an aggregate data
bandwidth of 80Mb/sec, matching typical proprietary configuration
data rates. With just eight (8) like PCBs in the system, the FPGA
configuration speed over the serial PTC bus is 160Mb/sec exceeding
the highest 8 bit wide configuration data bandwidth.
As the system complexity
continues to increase, functional testing as the sole means of
verifying product quality is becoming more complex and more
expensive. Testing and
diagnosing faults on high-speed differential signal, gigabit SERDES
connections for jitter, noise, and crosstalk is a challenging task
to accomplish with CPU based diagnostic software. Diagnosing backplane
problems to the pin is not possible without 1149.1 assisted
structural test.
Prudent OEM's are designing DFT into their multi-board
systems to enable this PCB to PCB interconnect testing and 1149.1
assisted BIST functions.
"We see IEEE 1149.1 as the
test and maintenance bus used throughout the system to enable
comprehensive system test and in-the-field updates", said CJ Clark,
Intellitech CEO and past IEEE 1149.1 chairperson. "IEEE 1149.5 has
been withdrawn as a standard, as it didn't address these issues or
allow for scalable multi-vendor PCB test and configuration." "In the past, serial EEPROMS
and FLASH were updated in the field over several separate functional
busses. This added to the complexity of the system and the
engineering involved.
Today, OEMs are seeking to lower their overall product cost
with a unified approach to in-the-field updates and multi-PCB
test. The PTC is the
first IC of its kind to address this problem", he
added.
The PTC was first designed
into a customer system back in 2000, this early adopter now has
systems deployed with up to 25 PCBs, each using a PTC and connected
over the patent-pending parallel test bus. The details of this
success will be published in a future press
release.
Key
features
* Creates a flexible,
scalable bus over standard 1149.1 for programming
FPGAs
* Provides design independent
infrastructure for updating non-volatile memory in a multi-board
system, from a centralized
point
* Enables simultaneous
parallel test of similar PCBs in-system
* Enables system level JTAG
test and FPGA configuration data rates of over
40Mbits/sec
* Enables reusable PCB to PCB
interconnect tests over the backplane
* Supports board
identification of multi-vendor PCBs in the
system
* Support for 4 to 8 local
JTAG paths per PTC with programmable voltage
levels
More information can be found
at http://www.intellitech.com/products/cjtag-system-sjtag-scanbridge.asp
Pricing and
Availability
The Intellitech PTC IC is
available now from stock.
The PTC is available in VQ100, TQ144 and 256 pin BGA packages
starting at $11.00 each in 10K quantities. Contact Intellitech at http://www.intellitech.com
for various options. A reference design with 4 cPCI boards, cPCI backplane, power
supply, complete with schematics and FPGA design files is available
for$4,500.00
Intellitech is a registered
trademark of Intellitech Corp.
PTC and the Parallel Test Bus is a trademark of Intellitech
Corp.