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Infrastructure IP Backgrounder

Standard Solutions for Configuration and Test of Boards and Systems


     "Intellitech’s Parallel Test Bus provides us with a system level test architecture that is important for the reliability and quality we need in our products.”     
Pete Marconi 
VP of Systems Engineering
 Axiowave Networks
    

 

Current Market Drivers

Advances in semiconductor technology, more powerful design automation tools, together with increased market competition, have driven design engineers to achieve higher levels of product integration with shortened development cycles. Customer expectations are that next generation products will have improved performance, more advanced features and cost less when compared to the generation of products they replace. This situation creates significant challenges for engineers to design systems with higher performance and increased functionality while at the same time reducing their manufacturing costs and shortening time-to-market.

Growth in Programmable Architectures

Another impacting issue facing design engineers is the market's desire for configurable products. Continuously changing industry standards and the need for field upgrades and repairs are becoming common requirements for new products. As such, a growing number of new designs utilize programmable logic devices, such as FPGAs, CPLDs, and non-volatile EEPROM and FLASH memories. Programmable silicon is enabling remotely upgradeable and programmable system logic. However, obtaining the access to all of the programmable devices in a complex system is increasingly becoming more difficult, especially for PCBs with mezzanine cards or multi-PCB backplane based systems. For the system designer, these challenges add to the costs and effort required to develop and later to manufacture, such configurable products. To support this, the designers must create their own ad-hoc functionally based methods and circuitry for remote debug, configuration and test.

Physical Access is Challenging for Systems Designers

Advanced device packaging such as ball grid arrays (BGAs), along with the demand for product miniaturization, has made physical access to nets on PCBs and systems either extremely difficult, or simply impossible. As a result, traditional methods of physically probing interconnect for the purposes of prototype debug, manufacturing test and in-system device programming/configuration is no longer possible. To further compound the problem, high clock frequencies and data rates, that come with increased performance and high speed serial interconnects, also prevent physical probing due to signal integrity concerns. Finally, the number of nets on an average PCB is growing beyond the capabilities of Automatic Test Equipment.

Semiconductor Designers have Confronted the Issue of Access

Complex PCBs and systems mimic the characteristics of an IC - physical access to nets is only available at the periphery. Board and system designers are now confronting many of the same issues as IC designers have faced for years at the chip level. To overcome the challenges, the IC designer turned to on-chip infrastructure IP. Yield and test concerns with very deep-sub micron semiconductor technologies forced chip designers to incorporate infrastructure IP into their designs to assist with silicon debug, to improve test quality and manufacturing yields. Examples of such infrastructure IP include Built-in-Self-Test (BIST) for logic and memories, Built-in-Self-Repair (BISR) for embedded memories, embedded core test logic for SoCs, and embedded timing analysis circuitry.

The IP infrastructure is dedicated circuitry, which is separate from the functional circuitry of the IC design. It is easy to implement and can be re-used from one design to the next. The IC designer spends little time manually designing strategies for scan-based test. Design automation has facilitated the use of such IP infrastructure and the IC design-for-test effort has been greatly reduced.

Another Lesson Can be Learned from Semiconductor Designers

Functionally testing complex PCBs and systems using customized software will yield the same results seen by IC designers in the early 90s - low fault coverage and long test development times. A common approach for system designers has been to embed tests developed by test engineers and systems designers on-board the product (e.g., stored in the CPU's FLASH memory). These "embedded tests" are used as a means to test the integrated systems, both in manufacturing and in the field. These functional test programs are ad-hoc, custom, embedded software applications. They require sophisticated resources to develop, validate and maintain, which result in higher product development costs. Quality managers cannot deterministically measure the fault coverage of functional tests. Significant resources can be invested in functional test and if they cannot identify or isolate faults in the field to repair a failing PCB they offer little value beyond running the system in mission mode. Functional tests also require a (mostly) working system in order to execute so they offer limited value in system-bring up and debug. As systems continue to grow more complex, it is becoming impractical to continue with this approach, just as it IC designers found out when they attempted to test their digital ICs with functional software.

A standard Configuration and Test Methodology is Needed

Systems will need to be designed to meet the requirements of remote configuration and test. Success in the market requires that sound methods be developed to support test and configuration throughout the life cycle of a product. Without the proper up front consideration, only ad-hoc methods will be possible and lessons learned from the IC world will be forgotten. The methods and strategies used for configuration and test play an important role in determining if a particular configuration and test solution will be cost effective.

Infrastructure IP for PCB and Systems

While there are standard methodologies today at the device level for test and configuration there is a need to have a standard approach to accessing these devices on complex boards or in multi-board systems. To support this, off-the-shelf, plug-and-play IP, which provides for a scalable in-system configuration, debug, and test infrastructure that is automatically understood by external ATE, is needed. This will enable system designers to build in the field re-configurable and high quality self-testable products with a minimum of engineering time and effort. Furthermore, a unified approach to test and configuration will enable designers of these field adaptable products to lower their manufacturing test costs, field support costs, and extend their products' useful life. Infrastructure IP for the board and system level will save engineering time and will reduce design risk - since the PCB and system configuration and test details are pre-engineered and leverage industry standards such as IEEE 1149.1 and IEEE 1532. The solutions can be made to be scalable and re-usable, during all phases of the product life cycle, and from one product design to the next.

Intellitech approach - Structured Embedded Configuration and Test

The Intellitech approach provides a structured methodology and flexible Infrastructure IP for embedding configuration and test at the board and system level to take advantage of cost efficiencies over the entire product life cycle. This reduces the design time for engineers, decreases test-engineering development and shortens test execution time. By including dedicated - IP has no mission mode role -- infrastructure IP in products, board and system designers can simplify in-system device configuration while enabling comprehensive structural test throughout the system. This embedded approach provides the design and test engineer with a scalable and reusable methodology, which augments existing industry test and configuration standards such as IEEE 1149.1 and IEEE 1532. The architecture of Intellitech's infrastructure IP was developed with the following objectives:

  • The infrastructure is completely scalable and reusable at any level of integration
  • Supports anytime/anywhere testing and in-the-field re-configuration for an entire multi-PCB system
  • Provides for scalable, parallel test and configuration to reduce reconfiguration times in the field and eliminate throughput bottlenecks in production test.
  • Offers a foundation of high-fault coverage structural test from which to build functional test and diagnostics firmware on
  • Supports in-system at-speed interconnects testing without the signal-integrity problems associated with ICT fixtures
  • Automates the creation and validation of embedded tests and configurations
  • Provides for reuse of configuration, debug and test at anytime during a product's life cycle
  • Provides patented on-board programming of non-volatile memories at datasheet speeds
  • Provides patented parallel test and programming of PCBs and ICs
  • Reduces or eliminates the need for physical access

Infrastructure IP

To implement the Intellitech embedded configuration and test methodology we provide the TEST-IPTM family of patent-pending infrastructure IP. The IP may be delivered as embeddable cores, or as integrated designs that engineers can simply design into the board and system levels of their products. The basic building blocks include a board level scan ring linking device (SRLTM), an embedded configuration and test processor (SystemBISTTM), a system level scan access device(PTCTM) and a fast access controller (FACTM) for programming and testing memories.