It's that time of year again, the International Test Conference in Santa Clara, CA is being held the week of October 27th. It's a special time of year for us, we look forward to seeing friends, some we have known for twenty years and some we will make as new friends this ITC. It's the time of year we like to show many of the innovations we have been working on that solve challenges you have and even ones you may not have anticipated. And this year is no different. It's also a time to say thank you to all of our dedicated customers for without you, we would not be able to do what we do - we would not get the challenges we enjoy working on everyday.


Today's economic environment is challenging, you don't have to read the newspapers to know it. Managers and engineering teams continue to be asked to do more with less resources - less engineers, less budget, less time while SoC, FPGA and PCB complexity continue to rise. Purchasing a JTAG tool is not a solution, at best it is a step in the right direction. Intellitech focuses on lowering product costs through IEEE 1149.x and other standards. Notice we wrote product costs not just 'test costs'. Our solutions and methodologies lower the cost of deploying complex electronic products, which maybe acheived through 'reduced engineering touch time', reducing BOM cost, reducing test cost, reducing cost at the CM, reducing cost for debug, reducing cost for field returns or other methods.


Maybe it's time you took a look for yourself?


Come to Intellitech’s ITC booth 218 to learn more about the following. Not attending? Please register on our website here: Contact Me

UltraTAP®-BT - Wireless JTAG test over Bluetooth®.  The convenience of Bluetooth that you get with your personal devices is now making JTAG test more convenient. UltraTAP-BT is about the size of a USB drive stores your JTAG/1149.1 tests, executes them and stores the failing results. Use Intellitech's software or 3rd party 1149.1/1149.6/JTAG tools to develop tests or FPGA/CPLD configuration data. The JTAG data is downloaded over USB to Intellitech's UltraTAP-BT. The UltraTAP-BT pod can be seperated from the USB connection and plugged onto the JTAG header and powered by your UUT. Tests are executed at UUT power-up or they can be commanded over Bluetooth or over RS-232. Bluetooth is a networkable protocol enabling UltraTAP-BT to be commanded from 30 meters away or from remotely networked PCs. Green/Red Pass/Fail LEDS are provided for manual operation and visual indication of the test. Test results are stored on UltraTAP-BT and can be retreived later or over the Bluetooth connection for register/pin/net level diagnostics. Intellitech's Mercury Remote Diagnostics software (see beloew) executes the pin/register/net level diagnostics from the stored failures no different and with no less accuracy than the diagnostics available with traditional PC hosted JTAG pods. What people are surprised to see is that since there is no CPU in UltraTAP-BT and no software or bus overhead of the PC, tests execute faster than they can be executed with a $15,000 PCIe card and JTAG POD.

UltraTAP-BT removes issues with JTAG cabling to distant PCBs, environmental noise on JTAG cables, operator error, software crashes and other problems related to PC based hosts. A pre-programmed UltraTAP-BT enables fool-proof execution of tests with minimal operator training. Using several UltraTAP-BT pods, pre-programmed with tests, manufacturing floors can now test low volume high mix products efficiently and cost effectively. UltraTAP-BT is based on Intellitech's patented SystemBIST technology.

SystemBIST SB4 - Flexible FPGA configuration device with JTAG self-test. Intellitech's fourth generation device adds high-speed parallel FPGA configuration for Xilinx and Altera devices, watch-dog support, programmable POR, SPI interface for CPU control and FPGA updates and tight integration with Intellitech's Mercury Remote Diagnostics Manager. SystemBIST enables decision-based FPGA programming - flow control on what FPGA bitstreams get loaded based on user programmable conditions. It also provides ‘failsafe’ in-the-field FPGA updates and PCB level JTAG self-test – something a configuration prom and your in-house method can’t do.  SystemBIST’s patented capability enables your company to eliminate returned PCBs with No Fault Found (NFF) - in the field test results are stored in non-volatile memory which can then be used with the MRDM (see below) to diagnose failures to the register/net/pin level.

FPGA devices have 85 million bits or more of configuration data, a JTAG only approach such as using STAPL or JAM and a JTAG controller just isn't fast enough. SystemBIST provides fast FPGA configuration over the 8 bit parallel configuration bus and uses JTAG for test, CPLD updates. We know what you're thinking. The engineer down the hall said that adding parts to the PCB is too expensive and he doesn't have the real estate. That maybe true if your PCB is a cell phone or PDA; those boards can be tested better with our PT100 or PT100Pro. However, if you have an FPGA based PCB, SystemBIST removes parts from the PCB - configuration devices, watch-dog timers, serial eeproms, power on reset circuits and reduces bitstream storage size. Intellitech's Eclipse software imports your JTAG tests (yes, even 3rd party generated tests) and build your test and FPGA configuration strategy. Eclipse let you define the flow control and lock critical bitstreams for failsafe updates. SystemBIST's embedded test technology lowers company's engineering time designing ad-hoc methods for FPGA programming and updates, lowers test costs with the on-board tests and reduces field service costs since the tests can be run in the field without PC based equipment. SystemBIST.

Intellitech Scan Ring Linker. Link eight seperate multi-voltage JTAG rings together on your PCB. SRL has more rings, lower unit cost, wider voltage ranges and higher achieveable PCB level TCK frequency than a Scansta112 or 74LVT8997. What more needs to be said? Scan Ring Linker.

Mercury Remote Diagnostics Manager. The MRDM increases tester throughput by enabling the tester to perform back-to-back testing without the need to stop to perform diagnostics on failing UUTs.  In contrast, 1149.X/JTAG tests performed by in-circuit testers and JTAG pods require running diagnostics in-line consuming valuable time and limiting throughput.   ICT and JTAG pods typically wait to analyze the data and record failure information before being able to start a test on a new UUT.  The MRDM supports collecting data and diagnosing failures for any IEEE 1149.1, 1149.6 or on-chip instrument based test, active or passive analog test, scripted or vector-based test, or any emulation based functional test performed by Intellitech's UltraTAP-BT, SystemBIST, PT100 or PT100Pro concurrent testers.   All diagnostics and failure information is collected and calculated without user intervention by the MRDM software service running on centralized or distributed network computers.   The software reduces test time and licensing costs for OEMs and contract manufacturers testing either a low-volume-high-mix of products or a high-volume-low-mix of products.

Concurrent Emulation Test+Analog+JTAG+FLASH programming.   Panelized PCBs that require serial programming and functional test are a challenge for memory-behind-pin (ask us why) testers like In-circuit test. Learn about Intellitech's PT100 Concurrent JTAG (CJTAG) tester and the PT100Pro concurrent combinational tester. The PT100 and PT100Pro enables concurrent test and programming for complex PCBs in panels or individual circuits. You're no longer limited to JTAG testing just one PCB at a time. PT100. The PT100 is the basis for a custom concurrent JTAG tester and the PT100PRo is a complete ready-to-run test platform with VG mass interconnect fixture interface. The PT100Pro has configurable internals that allow it to support testing for one to thirty-two PCB simultaneously. It performs powered-off analog tests, JTAG/1149.1 based testing, on-chip and on-PCB flash programming for parallel or serial devices and CPU-focused at-speed tests over JTAG. Use traditional pogo-pin fixtures from Intellitech, ECT or your preferred fixture provider. PT100Pro.

JTAG based At-speed SERDES and DDR tests

Intellitech’s Eclipse family of PCB Test, FPGA configuration and FLASH programming tools support at-speed testing of Xilinx Rocket I/O and DDR2 memories. (Ask us about DDR3 memories). Intellitech's on-chip Bit-Error-Rate Instrument BERT-IP provided IJTAG capability before it became the latest buzzword. Virtex5 and Virtex4 FPGAs don't have boundary-scan test on the high-speed pins and unfortunately don't have working 1149.6 AC coupled test capabilities either. If you don't have Intellitech's BERT-IP, your high-speed FPGA pins are not being tested. Functional tests not pinpointing the problems for you?  Get plug-n-play at-speed BERT tests for SERDES connections and DDR memories with robust diagnostics and without the headaches. Tests can be added to SystemBIST IC for in-the-field BER tests. BERT-IP.

In-Situ Silicon Debug

Intellitech's NEBULA Silicon Debugger gives you visibility into your silicon during the critical bring-up phase.  NEBULA’s integrated net and gate level diagnostics for TetraMAX® and Encounter® Test reduces the amount of time spent debugging SoC and IC test vectors from weeks to less than a day.  Using Intellitech’s reduced pin strategy; these IC tests can also be executed in the field with SystemBIST (above).Once structural tests have been validated, begin functional debug with NEBULA’s scan-chain dump capability.  Dump scan-chain and memory data after critical events and failures.  The scan-chain information and internal memory data is then brought into the simulator, effectively saving millions of clock cycles of simulation.  NEBULA Silicon Debugger





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