ICT in-circuit pcb test boundary scan





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Durham, NH 03824

PH:   (603) 868-7116

FAX: (603) 868-7119


For more information, contact:

Kareen Lefoley

Tel.   603.868.7116x106

Fax.  603.868.7119

  P R E S S  R E L E A S E

Intellitech presents techniques for PCB Self-Test, At-speed Xilinx Rocket I/O tests, At-speed DDR memory tests and more at ITC Test week Nov. 6-10


Durham , NH -- (BUSINESS WIRE) – October 21, 2005.  – Intellitech Corporation, http://www.intellitech.com , the technology leader in scan-based configuration, debug and test solutions today announced their schedule for advanced topics at the International Test Conference in Austin , Texas the week of November 6 th . Intellitech is presenting a full day of presentations on how major OEMs (Original Equipment Manufacturers) can lower their costs with solutions from Intellitech Corp. Highlights of the advanced topics are embedded structural PCB tests, at-speed testing of gigabit Xilinx RocketIO, PCB level at-speed testing of DDR memories, designing PCBs with multiple scan-chains, basic DFT for TAP based silicon debug, concurrent JTAG and test techniques for managing high volume PCB test without running par all el in-circuit testers. The special events are as follows, interested parties can register at link removed. There is no charge for any of the events.


Sunday, November 6 th , 2005

3:10PM-4:00PM GPIB/PXI w/ 1149.1 and Eclipse

6:00PM-7:30PM Cocktail Reception

Monday, November 7 th , 2005

8:15AM-9:30AM PCB scan-chain design – what to do with high-fanout, multiple scan-chains and different TAP voltages

10:30AM-11:30AM DFT for TAP based in-situ functional silicon debug

12:50PM-1:45 PM Basics of 1149.1 based board/system level at-speed (.5-10Ghz) tests of Xilinx Rocket I/O Interconnects.

2:00PM-2:50PM Concurrent JTAG – Massively concurrent testing over standard 1149.1/JTAG interface (for ICs and PCBs)

3:00PM-4:00PM Limitations of 'standard' Multi-drop 1149.1 for multi-pcb systems

4:15PM-5:15PM Basics of 1149.1 based board/system level at-speed tests for high-speed DDR Memory interconnects

Tuesday, November 8 th , 2005

3:10PM-4:00PM PCB Test time too long? What can you do?

Wednesday, November 9 th , 2005

3:10PM-4:00PM Is boundary-scan on In-circuit Testers the right solution for you?

Thursday, November 10 th , 2005

1:30PM-4:00PM SystemBIST – Platform FPGA Configuration with Embedded PCB Self-Test


About Intellitech

With over 16 years of experience, Intellitech is the most trusted name in scan-based configuration, debug and test. Intellitech's patented infrastructure IP, the TEST-IPTM family enables embedded test, debug and configuration of IC's, PCB's and Systems. Intellitech's proprietary solutions enable customers to build easy-to-debug, self-testable and in-the-field re-configurable products. The unified debug, test and configuration approach enables customers to a chie ve shorter time-to-volume, lower manufacturing test costs, provide field adaptable products and enable in-the-field system self-test.


Intellitech is a registered trademark of Intellitech Corporation. SystemBIST, Concurrent JTAG, CJTAG, TEST-IP and “The Infrastructure IP company” are trademarks of Intellitech Corporation . All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.