High-Quality PCB Interconnect Tests with Eclipse Board Interconnect ATPG
The Eclipse Virtual Interconnect Test
(VIT) package is a comprehensive test and diagnostic solution for
developing high fault coverage tests for PCB's that are IEEE 1149.1
compliant.
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VIT automatically creates test
patterns for interconnect wires between boundary-scan devices
with single-ended and differential drivers/receivers.
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JTAG/1149.1 Interconnect Overview
The EDIF netlist from industry standard CAD systems defines the PCBs connectivity and the pin properties of all devices in the design. Having this information and netlist-based constraint checking is essential to not inadvertently damage devices during debug. IEEE BSDL models for each scan device describe the boundary-scan architecture for each device. The DCD2 file defines the scan chains(s) order.
The Eclipse Virtual Interconnect Test engine automatically creates test vectors for all 1149.1 based PCB defect types. These include, stuck-at ('1', '0'), opens and shorts. Eclipse VIT can also test today's complex high-speed point-to-point differential signals (series and termination resistors are tested with VIT).
VIT generates tests vectors, for scan and non-scan devices, and writes the test data out in industry standard Serial Vector Format (SVF). SVF describes Instruction and Data Register scan operations without the detailed TAP state transitions. VIT generates a fault coverage report. The report lists the fault coverage in terms of a percentage and catalogs the detected and undetected faults by name.
VIT
produces diagnostic support data in one of two formats. The most advanced format is the expect data file. This option describes the expected behavior of a good board during the virtual interconnect test and is used by the advanced BSID diagnostic engine. Optionally, there is a more detailed level of diagnostics available called Boundary Scan Intelligent Diagnostics (BSID). The BSID engine performs analysis that is more exhaustive; reports fault information to the pin and net level and identifies the type of fault that may be occurring -- short, stuck-at, or opens.
By default, VIT produces a dimplier optimized diagnostic lookup table. This is an ASCII file that lists which net is faulty for all possible types of failures that could occur during the virtual interconnect test.
SVF data is applied to the Unit Under Test by Eclipse. Schematic Logic ProbeTM (SLPTM) and Virtual Fault AnalyzerTM (VFATM) are used to help isolate PCB failures. These tools are available with the Eclipse Test Development System and the Eclipse Scan Executive Test Station.
VIT Features
- Robust fault model support including:
stuck-at ('1', '0'), opens and shorts and point-to-point differential signals (series and termination resistors are tested)
- Support for hierarchical netlists and multi-PCB systems without 'netlist merging'
- Optionally, constrain pins to accommodate special design cases
- Fast fault diagnosis and isolation with
SLP and VFA
- Optional MCM and multi-board support without netlist
modification using CircuitMergeTM
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