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Boundary Scan JTAG

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Standard Features:

BSDL Library
Schematic Debug
» Visual Fault Analysis
» Timing Diagram
» TCL Scripting Language

Tests & Programming
Scan Path Test
Interconnect Pin Fault
Memory Test
» FLASH Programming
» ScanWorks®

Analog Instrument
VISA Instrument Control
GPIB IEEE 488 Control

1149.1/1149.6 Interconnect
Interconnect Diagnostics
Vector Translator
C++ and Libraries
LabView Interface
Network Licensing

WGL Vector Support
VCS Sim Interface

Hardware Options:

UltraTAP JTAG Controller
PT100Pro Production Tester
PT100 Multiport JTAG
RCT Benchtop Tester
32 bit PCI Card Tester
PC Printer Port
Altera Byteblaster

» Eclipse Brochure

» Eclipse Family Overview
» Test Development
» Manufacturing Test
» Diagnostics and Repair

Boundary Scan Intelligent Diagnostics (BSID) Overview

The Eclipse Virtual Interconnect Test (VIT) ATPG package creates test vectors and advanced diagnostics. There is an option available for The Eclipse Test Development Environment that supplies advanced diagnostics called Boundary-Scan Intelligent Diagnostics (BSID).

When a boundary-scan test fails, BSID uses the failure data generated by VIT and the actual digital test results returned from the Unit Under Test (UUT) to isolate the failing devices.

Eclipse Status Window Displaying Diagnostics

How BSID works

BSID requires two inputs; the diagnostic database supplied by VIT and the digital test failure data (DTFD) returned by the Intellitech Test Hardware from the UUT. The diagnostic database produced by BIT contains information about the UUT: the netlist, the scan path, and the scan vectors.

The DTFD is an ASCII-format file, retuned by the Intellitech test system, that identifies the tester pins that failed and the failing pattern number.

BSID diagnostics

VIT tests can fail under a variety of conditions. BSID diagnoses the following failure types. In all cases, BSID states the problem, lists all inputs and outputs on the net, and identifies the failing detect points.

Stuck at failures

All inputs on a net are stuck either at logic 1 or logic 0. Typically, the problem is an open on the net or the net is shorted to power or ground.

Some inputs on a net are stuck either at logic 1 or logic 0. This condition typically results from an open on the part of the net that connects the stuck input(s).

Net is stuck either at logic 1 or logic 0 only when a particular driver is active. Most often, the problem is an open at the specified driver lead on a bus.

Stuck-at Fault

Shorts between nets

Common bridging faults between nets are clearly diagnosed. Many testers and simulators accept truth by BSID regardless of whether a logic 1 or a logic 0 wins.

Short Fault

Strong driver short

Typically, a high current driver or a tester pin is shorted to some other net(s). The problem is that the net with the strong driver never fails because it overdrives other net(s) involved in the short.

Faulty bi-directional pin

A blown input or output driver at the bi-directional pin typically causes this failure type. As a result, the boundary-scan output cell for the bi-directional pin drives the correct data onto the net but its associated boundary-scan input cell does not capture the correct value. Alternatively, the boundary-scan input cell captures the correct value from other drivers on the net, but its associated boundary-scan output cell is not able to drive the net.

Extended stuck-at faults

Leaky bus drivers can cause a test to fail by overdriving the active driver on a bus. Shorts between boundary-scan nets and non-boundary-scan nets. As part of an in-circuit test program, BIT Plus patterns can detect shorts between boundary-scan nets that have no tester access and non-boundary-scan nets with tester access.


  • Automatic diagnosis of Eclipse VIT ATPG and VCCT test failures
  • Can be run on the tester or at an off-line repair station
  • Currently available for Teradyne board test systems and Intellitech test systems
  • Transportable to other test systems