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Thank you for your interest in Intellitech's ITC events and activities. We are pleased that you are interested in attending one or more of the events.
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Please select the Intellitech events you would like to attend by checking the box to the left. Events start Monday October 23, 2006. Meetings and events are at Alameda Room, Hyatt Regency next to the Santa Clara convention center.

1	Mon	8:15AM	-	9:00AM	GPIB/PXI w/ 1149.1 and Eclipse Explore how to maximize test coverage on your PCB outside of the digital domain.
2		9:30AM	-	10:15AM	Using PCB EDIF for Fast-accurate ATPG A netlist is a netlist is a netlist. Or is it? Find out how to ease the flow from design to 1149.1 automatic test pattern generation.
3		10:45AM	-	11:30AM	Linking multiple scan-chains on PCBs. Introduction to PCB scan-chain design. This session explores what to do with high-fanout, multiple scan-chains, different TAP voltages and multiple daughter-cards with 1149.1 test needs.
4		1:00PM	-	2:00PM	Concurrent JTAG - concurrent test for 1149.1 1149.1 gets a bad rap for being 'slow' - too slow for IC and PCB test. See how Concurrent JTAG can increase your throughput without costing more in test equipment.
5		2:15PM	-	3:15PM	SystemBIST - PCB self-test in minutes Intermittent faults causing you problems? False alarms and false failures from functional test in the field? Learn more how SystemBIST can provide you with structured scan test - anywhere/anytime. Reduce your NTF (No Trouble Found).
6		3:30PM	-	4:15PM	DFT for TAP based functionalvector debug Learn the basics of what you need for successful in-situ silicon debug through the 1149.1 TAP.
7	Tue	10:30AM	-	11:00AM	PCB Test Myth Busters Seems lots of decisions about PCB test are made these days, based on incorrect assumptions and old-school rules. How do they hold up? This session holds up a few of the test mantras to the light.
8		11:10AM	-	12:00PM	At-speed SERDES/DDR Test with 1149.1 Huh? How can slow-speed 1149.1 test Gigahertz speeds? Get the basics on how to solve the test complexities these technologies bring to FPGA based PCBs.
9		4:00PM	-	4:45PM	System level 1149.1 solutions What are the limitations of 'gateway' devices (ASP, ScanBridge, etc)? Find out the best test architectures for passive backplane based systems that require an 1149.1 test strategy.
10		5:00PM	-	5:45PM	How to achieve zero digital test time. Come on, can we really test PCBs without being affected by test time? 1149.1 test and programming test times continue to increase, becoming the bottleneck in the production line. Find out the solution that shifts your throughput limitations to handling-time and not test time.
11	Wed	1:45PM	-	2:30PM	Is boundary-scan on ICT the right solution for you? Where's the best place to perform boundary-scan? The answer may surprise you.
12		2:45PM	-	3:30PM	Test Engineers - show PCB designers new ways for FPGA configuration and get JTAG self-test for you. Learn some of the basics of SystemBIST for FPGA configuration and contribute to the design team. Advanced configuration devices can help your FPGA/PCB designer and enable you to get PCB JTAG self-test for production and the field.

About the presenters Dr. Bernd Koenemann's professional career includes positions as Chief Scientist at Mentor Graphics, Fellow at Cadence Design Systems, Distinguished Engineer at IBM, Vice President at Logicvision, as well as Engineering Fellow at Honeywell. During his career he pioneered and contributed to the practical introduction of modern scan test data compression, advanced delay test generation with integrated timing, and logic Built-In Self-Test. In addition, he proposed and helped launch the Core Test Language (CTL) effort that is now incorporated in the IEEE 1450 standard. Dr. Koenemann is the author and coauthor of multiple technical papers and presentations, and he is the inventor and coinventor of multiple patents in the area of DFT and test. He was the invited keynote speaker at several major conferences and workshops, including the International Test Conference (ITC), and recently contributed a chapter on DFT to a handbook on Electronic Design Automation (EDA). Dr. Koenemann holds PhD degree in Theoretical Physics from the Technical University Braunschweig, Germany

CJ Clark was the elected chairperson of the IEEE 1149.1 JTAG working group from 1996 to 2002. He has been active in other IEEE working groups and has presented at International Test Conference, TECS (Testing Embedded Cores-Based Systems) Workshop, the Board Test Workshop, Ottawa Test Workshop and VLSI Test Symposium. CJ serves on the University of New Hampshire College of Engineering and Physical Science (CEPS) Advisory Board. He also serves on the UNH Department of Electrical Engineering Advisory Board and is a frequent guest lecturer. He is co-inventor on two US, two Canadian, one Taiwanese patent with others pending world-wide. His first job in test was in 1978 with Plantronics/Wilcom.

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