Intellitech Corporation                          

60 Rochester Hill Rd. Ste 7

Rochester, NH 03867

Definitions

BIST -  Built In Self-Test.  Logic designed to perform a test and return a result with minimal stimuli from outside the IC.

BERT - Bit Error Rate Test.  A test for high speed SERDES serial channels which calculates the rate at which bits are failing.  A good channel may tolerate some bits that fail.

BSDL -  Boundary Scan Description Language.   A formal description language for scan registers that has been part of IEEE 1149.1 since 1994.  1149.1-2013 expands the use to enable hierarchy for on-chip internal registers and IEEE 1500 structures.

DDR - Double Data Rate

FPGA - Field Programmable Gate Array

IEEE  -  Institute of Electrical and Electronic Engineers

Infrastructure IP -  On-chip IP which are Design-for-Yield and Design-for-Test structures used for enhancing yield, enhancing IC test or performing external IC ecosystem test at the system level.

JTAG - Joint Test Action Group.  The original group of engineers in the 1980s who developed the basics of the proposal for P1149.1, ratified first in 1990.

SERDES - Serializer/Deserializer.   SERDES is an acronym typically used to describe generically high-speed serial input/output on a chip.   PCIe and USB 3.0 are examples of SERDES.

SoC - System on a Chip.

TAP - Test Access Port.  The dedicated serial port on all IEEE 1149.1 compliant pins which gives access to all scan based structures.

Tcl - Tool Command Language