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1
The slide guide is available in the following file:
slidesV5.3.ppt: PowerPoint 2000 format.  Viewable also
with PowerPoint ’97.
2
“Today’s System is tomorrow’s IC”.  Let’s learn about IC test history and how it can help System Test
Reviewing IC test history can help to understand where PCB and System Test methodologies are today and the direction they will go in the future. The dates that will be shown are just generalizations on the industry, some companies will have different time lines.
1970s to Mid-1980s  Functional Test dominated digital IC test methods.
However, increasing functional test development times and decreasing stuck-at fault coverage drove development of  internal scan chains that were inserted in the IC design.  Internal scan enabled  ATPG (Automatic Test Pattern Generation) tools to generate test patterns for high stuck-at fault coverage.
Many companies/vendors using ‘ad-hoc’ approaches and non-structured DFsT such as ‘partial scan’.  At-Speed tests  were normally performed with Functional Test. Some companies (HP, IBM) have advanced methods for at-speed tests using path-delay tests
Late 90s-2000 – All companies using ‘partial scan’ gone. All digital IC test include structural scan-based test for stuck-ats.  Scan infrastructure in IC is standard.  BIST
2000-Present – Test times (due to IC density) and capital equipment costs have driven embedded IC test (BIST).  IC functional speeds surpass speed of ATE, hence on-board or scan-based at-speed structural test is adopted by many companies
Beyond -  More standardization on at-speed structural test either embedded or executed with low cost/low speed tester.   Noise, crosstalk, signal integrity test problems need to be solved.  Standards such as P1500 enable test re-use, so test vectors follow building blocks.
3
“Today’s System is tomorrow’s IC”.  Let’s learn about IC test history and how it can help System Test
Reviewing IC test history can help to understand where PCB and System Test methodologies are today and the direction they will go in the future. The dates that will be shown are just generalizations on the industry, some companies will have different time lines.
1970s to Mid-1980s  Functional Test dominated digital IC test methods.
However, increasing functional test development times and decreasing stuck-at fault coverage drove development of  internal scan chains that were inserted in the IC design.  Internal scan enabled  ATPG (Automatic Test Pattern Generation) tools to generate test patterns for high stuck-at fault coverage.
Many companies/vendors using ‘ad-hoc’ approaches and non-structured DFsT such as ‘partial scan’.  At-Speed tests  were normally performed with Functional Test. Some companies (HP, IBM) have advanced methods for at-speed tests using path-delay tests
Late 90s-2000 – All companies using ‘partial scan’ gone. All digital IC test include structural scan-based test for stuck-ats.  Scan infrastructure in IC is standard.  BIST
2000-Present – Test times (due to IC density) and capital equipment costs have driven embedded IC test (BIST).  IC functional speeds surpass speed of ATE, hence on-board or scan-based at-speed structural test is adopted by many companies
Beyond -  More standardization on at-speed structural test either embedded or executed with low cost/low speed tester.   Noise, crosstalk, signal integrity test problems need to be solved.  Standards such as P1500 enable test re-use, so test vectors follow building blocks.
9
“Today’s System is tomorrow’s IC”.  Let’s learn about IC test history and how it can help System Test
Reviewing IC test history can help to understand where PCB and System Test methodologies are today and the direction they will go in the future. The dates that will be shown are just generalizations on the industry, some companies will have different time lines.
1970s to Mid-1980s  Functional Test dominated digital IC test methods.
However, increasing functional test development times and decreasing stuck-at fault coverage drove development of  internal scan chains that were inserted in the IC design.  Internal scan enabled  ATPG (Automatic Test Pattern Generation) tools to generate test patterns for high stuck-at fault coverage.
Many companies/vendors using ‘ad-hoc’ approaches and non-structured DFsT such as ‘partial scan’.  At-Speed tests  were normally performed with Functional Test. Some companies (HP, IBM) have advanced methods for at-speed tests using path-delay tests
Late 90s-2000 – All companies using ‘partial scan’ gone. All digital IC test include structural scan-based test for stuck-ats.  Scan infrastructure in IC is standard.  BIST
2000-Present – Test times (due to IC density) and capital equipment costs have driven embedded IC test (BIST).  IC functional speeds surpass speed of ATE, hence on-board or scan-based at-speed structural test is adopted by many companies
Beyond -  More standardization on at-speed structural test either embedded or executed with low cost/low speed tester.   Noise, crosstalk, signal integrity test problems need to be solved.  Standards such as P1500 enable test re-use, so test vectors follow building blocks.
10
System Test can learn from IC test, where structured DFT was developed to reduce test development time through ATPG.
Like cores in the IC, Systems need to have a test architecture that is scalable and enables test re-use of manufacturing PCB tests.
Fault coverage at the system level can be measured where structured stuck-at tests and structured at-speed tests are used.
Reduce the test development time by layering 1149.1 structured tests with 1149.1 based at-speed tests.  Automatic test generation, and automatic and robust diagnostics
11
System Test can learn from IC test, where structured DFT was developed to reduce test development time through ATPG.
Like cores in the IC, Systems need to have a test architecture that is scalable and enables test re-use of manufacturing PCB tests.
Fault coverage at the system level can be measured where structured stuck-at tests and structured at-speed tests are used.
Reduce the test development time by layering 1149.1 structured tests with 1149.1 based at-speed tests.  Automatic test generation, and automatic and robust diagnostics
12
System Test can learn from IC test, where structured DFT was developed to reduce test development time through ATPG.
Like cores in the IC, Systems need to have a test architecture that is scalable and enables test re-use of manufacturing PCB tests.
Fault coverage at the system level can be measured where structured stuck-at tests and structured at-speed tests are used.
Reduce the test development time by layering 1149.1 structured tests with 1149.1 based at-speed tests.  Automatic test generation, and automatic and robust diagnostics
13
14
“Today’s System is tomorrow’s IC”.  Let’s learn about IC test history and how it can help System Test
Reviewing IC test history can help to understand where PCB and System Test methodologies are today and the direction they will go in the future. The dates that will be shown are just generalizations on the industry, some companies will have different time lines.
1970s to Mid-1980s  Functional Test dominated digital IC test methods.
However, increasing functional test development times and decreasing stuck-at fault coverage drove development of  internal scan chains that were inserted in the IC design.  Internal scan enabled  ATPG (Automatic Test Pattern Generation) tools to generate test patterns for high stuck-at fault coverage.
Many companies/vendors using ‘ad-hoc’ approaches and non-structured DFsT such as ‘partial scan’.  At-Speed tests  were normally performed with Functional Test. Some companies (HP, IBM) have advanced methods for at-speed tests using path-delay tests
Late 90s-2000 – All companies using ‘partial scan’ gone. All digital IC test include structural scan-based test for stuck-ats.  Scan infrastructure in IC is standard.  BIST
2000-Present – Test times (due to IC density) and capital equipment costs have driven embedded IC test (BIST).  IC functional speeds surpass speed of ATE, hence on-board or scan-based at-speed structural test is adopted by many companies
Beyond -  More standardization on at-speed structural test either embedded or executed with low cost/low speed tester.   Noise, crosstalk, signal integrity test problems need to be solved.  Standards such as P1500 enable test re-use, so test vectors follow building blocks.
15
“Today’s System is tomorrow’s IC”.  Let’s learn about IC test history and how it can help System Test
Reviewing IC test history can help to understand where PCB and System Test methodologies are today and the direction they will go in the future. The dates that will be shown are just generalizations on the industry, some companies will have different time lines.
1970s to Mid-1980s  Functional Test dominated digital IC test methods.
However, increasing functional test development times and decreasing stuck-at fault coverage drove development of  internal scan chains that were inserted in the IC design.  Internal scan enabled  ATPG (Automatic Test Pattern Generation) tools to generate test patterns for high stuck-at fault coverage.
Many companies/vendors using ‘ad-hoc’ approaches and non-structured DFsT such as ‘partial scan’.  At-Speed tests  were normally performed with Functional Test. Some companies (HP, IBM) have advanced methods for at-speed tests using path-delay tests
Late 90s-2000 – All companies using ‘partial scan’ gone. All digital IC test include structural scan-based test for stuck-ats.  Scan infrastructure in IC is standard.  BIST
2000-Present – Test times (due to IC density) and capital equipment costs have driven embedded IC test (BIST).  IC functional speeds surpass speed of ATE, hence on-board or scan-based at-speed structural test is adopted by many companies
Beyond -  More standardization on at-speed structural test either embedded or executed with low cost/low speed tester.   Noise, crosstalk, signal integrity test problems need to be solved.  Standards such as P1500 enable test re-use, so test vectors follow building blocks.
16
“Today’s System is tomorrow’s IC”.  Let’s learn about IC test history and how it can help System Test
Reviewing IC test history can help to understand where PCB and System Test methodologies are today and the direction they will go in the future. The dates that will be shown are just generalizations on the industry, some companies will have different time lines.
1970s to Mid-1980s  Functional Test dominated digital IC test methods.
However, increasing functional test development times and decreasing stuck-at fault coverage drove development of  internal scan chains that were inserted in the IC design.  Internal scan enabled  ATPG (Automatic Test Pattern Generation) tools to generate test patterns for high stuck-at fault coverage.
Many companies/vendors using ‘ad-hoc’ approaches and non-structured DFsT such as ‘partial scan’.  At-Speed tests  were normally performed with Functional Test. Some companies (HP, IBM) have advanced methods for at-speed tests using path-delay tests
Late 90s-2000 – All companies using ‘partial scan’ gone. All digital IC test include structural scan-based test for stuck-ats.  Scan infrastructure in IC is standard.  BIST
2000-Present – Test times (due to IC density) and capital equipment costs have driven embedded IC test (BIST).  IC functional speeds surpass speed of ATE, hence on-board or scan-based at-speed structural test is adopted by many companies
Beyond -  More standardization on at-speed structural test either embedded or executed with low cost/low speed tester.   Noise, crosstalk, signal integrity test problems need to be solved.  Standards such as P1500 enable test re-use, so test vectors follow building blocks.
17
“Today’s System is tomorrow’s IC”.  Let’s learn about IC test history and how it can help System Test
Reviewing IC test history can help to understand where PCB and System Test methodologies are today and the direction they will go in the future. The dates that will be shown are just generalizations on the industry, some companies will have different time lines.
1970s to Mid-1980s  Functional Test dominated digital IC test methods.
However, increasing functional test development times and decreasing stuck-at fault coverage drove development of  internal scan chains that were inserted in the IC design.  Internal scan enabled  ATPG (Automatic Test Pattern Generation) tools to generate test patterns for high stuck-at fault coverage.
Many companies/vendors using ‘ad-hoc’ approaches and non-structured DFsT such as ‘partial scan’.  At-Speed tests  were normally performed with Functional Test. Some companies (HP, IBM) have advanced methods for at-speed tests using path-delay tests
Late 90s-2000 – All companies using ‘partial scan’ gone. All digital IC test include structural scan-based test for stuck-ats.  Scan infrastructure in IC is standard.  BIST
2000-Present – Test times (due to IC density) and capital equipment costs have driven embedded IC test (BIST).  IC functional speeds surpass speed of ATE, hence on-board or scan-based at-speed structural test is adopted by many companies
Beyond -  More standardization on at-speed structural test either embedded or executed with low cost/low speed tester.   Noise, crosstalk, signal integrity test problems need to be solved.  Standards such as P1500 enable test re-use, so test vectors follow building blocks.