ICT in-circuit pcb test boundary scan





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Fax.  603.868.7119

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Record attendence for Intellitech tutorial at VLSI 2007


Durham, NH  Jan 18, 2007 —  Intellitech's half day tutorial on "Embedded Structural Test" set a new attendence record with over sixty managers and engineers attending. The tutorial was invited by the VLSI 2007 Test Conference organizers. Intellitech presented its unique approach to IEEE 1149.x standards showing attendees leading methods for PCB scan-chain design, PCB self-test, FPGA configuration, concurrent test with CJTAG, and System level boundary-scan design. Comments from attendees were positive that the industry is catching on to the Intellitech methodology that lowers product costs. Comments about the tutorial include:

“We’ve always thought of JTAG as either for emulation or a way the test guys reduce pogo-pins on ICT. This tutorial opened up our eyes as to how critical JTAG decisions must be made early during the architecture phase of the product to lower costs.”

“SystemBIST is a no-brainer, the parts cost is less than what I’m using for FPGA configuration and we won’t need to wheel a PC and JTAG pod up to the product to test it.”

"In recent years the IC industry has moved away from predominately functional test for ICs in favor of scan-based structural test for ICs, due to the increased design complexity. Structural scan-based test and BIST for ICs has shown to be advantageous because of the higher fault coverage with less cost and engineering time," said, CJ Clark, past chair of IEEE 1149.1. "Today this same migration is occurring in the PCB and system space, where structural test and scan-based BIST are reducing the burden of built-in functional test diagnostics. Managers are embracing the technology to lower the costs of functional diagnostics but at the same time get higher fault coverage, reduced engineering resources and eliminate the "No fault found" PCBs being returned from the field."