ICT in-circuit pcb test boundary scan





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Intellitech CEO speaks at the USPTO 2007 Examiner Education Program


Durham, NH April 2 , 2007 — Intellitech CEO CJ Clark spoke on scan-based test methods and the state-of-the-art in test to examiners at the United States Patent and Trademark Office. The speaking engagement was completed on March 27th. CJ Clark, said “It was an honor to appear before the USPTO, an organization with a 200+ year old history, the foundation of which was signed into law by George Washington in 1790. The examiners had a number of poignant questions relating to how IC and PCB level scan is used in the industry. I was able to share a fair amount of prior art for scan-based debug and test techniques that perhaps don’t have a lot of conference papers on them that examiners can use as prior art.” “I can now appreciate the scope of the work and work-load that the examiners manage each day.” Clark added. Gail Hayes, USPTO TC2100 Training Coordinator, said, “The feedback from the patent examiners on the value of the training was very positive. Our plan is to have CJ back in August for the 2007 Tech Fair to cover additional topics.” The examiner post-training survey included positive comments such as the following. “CJ’s presentation was right on the button. He mixed basic technical features and the future state of the art, and was extremely knowledgeable about everything that we as an art unit deal with every day.” CJ will return to the USPTO in August for additional follow up lectures on scan-based test and debug.